| Nicolas Le Bayon | d8f3b15 | 2024-01-24 13:08:42 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2025, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef STM32MP21_PWR_H |
| 8 | #define STM32MP21_PWR_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | #define PWR_CR1 U(0x00) |
| 13 | #define PWR_CR2 U(0x04) |
| 14 | #define PWR_CR3 U(0x08) |
| 15 | #define PWR_CR7 U(0x18) |
| 16 | #define PWR_CR8 U(0x1C) |
| 17 | #define PWR_CR9 U(0x20) |
| 18 | #define PWR_CR10 U(0x24) |
| 19 | #define PWR_CR11 U(0x28) |
| 20 | #define PWR_BDCR U(0x38) |
| 21 | #define PWR_CPU1CR U(0x40) |
| 22 | #define PWR_CPU2CR U(0x44) |
| 23 | #define PWR_D1CR U(0x4C) |
| 24 | #define PWR_D2CR U(0x50) |
| 25 | #define PWR_WKUPCR1 U(0x60) |
| 26 | #define PWR_WKUPCR2 U(0x64) |
| 27 | #define PWR_WKUPCR3 U(0x68) |
| 28 | #define PWR_WKUPCR4 U(0x6C) |
| 29 | #define PWR_WKUPCR5 U(0x70) |
| 30 | #define PWR_WKUPCR6 U(0x74) |
| 31 | #define PWR_RSECCFGR U(0x100) |
| 32 | #define PWR_RPRIVCFGR U(0x104) |
| 33 | #define PWR_R0CIDCFGR U(0x108) |
| 34 | #define PWR_R1CIDCFGR U(0x10C) |
| 35 | #define PWR_R2CIDCFGR U(0x110) |
| 36 | #define PWR_R3CIDCFGR U(0x114) |
| 37 | #define PWR_R4CIDCFGR U(0x118) |
| 38 | #define PWR_R5CIDCFGR U(0x11C) |
| 39 | #define PWR_R6CIDCFGR U(0x120) |
| 40 | #define PWR_WIOSECCFGR U(0x180) |
| 41 | #define PWR_WIOPRIVCFGR U(0x184) |
| 42 | #define PWR_WIO1CIDCFGR U(0x188) |
| 43 | #define PWR_WIO1SEMCR U(0x18C) |
| 44 | #define PWR_WIO2CIDCFGR U(0x190) |
| 45 | #define PWR_WIO2SEMCR U(0x194) |
| 46 | #define PWR_WIO3CIDCFGR U(0x198) |
| 47 | #define PWR_WIO3SEMCR U(0x19C) |
| 48 | #define PWR_WIO4CIDCFGR U(0x1A0) |
| 49 | #define PWR_WIO4SEMCR U(0x1A4) |
| 50 | #define PWR_WIO5CIDCFGR U(0x1A8) |
| 51 | #define PWR_WIO5SEMCR U(0x1AC) |
| 52 | #define PWR_WIO6CIDCFGR U(0x1B0) |
| 53 | #define PWR_WIO6SEMCR U(0x1B4) |
| 54 | #define PWR_CPU1D1SR U(0x200) |
| 55 | #define PWR_CPU2D2SR U(0x204) |
| 56 | #define PWR_DBGR U(0x308) |
| 57 | #define PWR_VERR U(0x3F4) |
| 58 | #define PWR_IPIDR U(0x3F8) |
| 59 | #define PWR_SIDR U(0x3FC) |
| 60 | |
| 61 | /* PWR_CR1 register fields */ |
| 62 | #define PWR_CR1_VDDIO3VMEN BIT(0) |
| 63 | #define PWR_CR1_USB33VMEN BIT(2) |
| 64 | #define PWR_CR1_AVMEN BIT(4) |
| 65 | #define PWR_CR1_VDDIO3SV BIT(8) |
| 66 | #define PWR_CR1_USB33SV BIT(10) |
| 67 | #define PWR_CR1_ASV BIT(12) |
| 68 | #define PWR_CR1_VDDIO3RDY BIT(16) |
| 69 | #define PWR_CR1_USB33RDY BIT(18) |
| 70 | #define PWR_CR1_ARDY BIT(20) |
| 71 | #define PWR_CR1_VDDIOVRSEL BIT(24) |
| 72 | #define PWR_CR1_VDDIO3VRSEL BIT(25) |
| 73 | #define PWR_CR1_GPVMO BIT(31) |
| 74 | |
| 75 | /* PWR_CR2 register fields */ |
| 76 | #define PWR_CR2_MONEN BIT(0) |
| 77 | #define PWR_CR2_VBATL BIT(8) |
| 78 | #define PWR_CR2_VBATH BIT(9) |
| 79 | #define PWR_CR2_TEMPL BIT(10) |
| 80 | #define PWR_CR2_TEMPH BIT(11) |
| 81 | |
| 82 | /* PWR_CR3 register fields */ |
| 83 | #define PWR_CR3_PVDEN BIT(0) |
| 84 | #define PWR_CR3_PVDO BIT(8) |
| 85 | |
| 86 | /* PWR_CR7 register fields */ |
| 87 | #define PWR_CR7_VDDIO2VMEN BIT(0) |
| 88 | #define PWR_CR7_VDDIO2SV BIT(8) |
| 89 | #define PWR_CR7_VDDIO2RDY BIT(16) |
| 90 | #define PWR_CR7_VDDIO2VRSEL BIT(24) |
| 91 | #define PWR_CR7_VDDIO2VRSTBY BIT(25) |
| 92 | |
| 93 | /* PWR_CR8 register fields */ |
| 94 | #define PWR_CR8_VDDIO1VMEN BIT(0) |
| 95 | #define PWR_CR8_VDDIO1SV BIT(8) |
| 96 | #define PWR_CR8_VDDIO1RDY BIT(16) |
| 97 | #define PWR_CR8_VDDIO1VRSEL BIT(24) |
| 98 | #define PWR_CR8_VDDIO1VRSTBY BIT(25) |
| 99 | |
| 100 | /* PWR_CR9 register fields */ |
| 101 | #define PWR_CR9_BKPRBSEN BIT(0) |
| 102 | |
| 103 | /* PWR_CR10 register fields */ |
| 104 | #define PWR_CR10_RETRBSEN_MASK GENMASK_32(1, 0) |
| 105 | #define PWR_CR10_RETRBSEN_SHIFT 0 |
| 106 | #define PWR_CR10_RETRBSEN_DISABLE 0U |
| 107 | #define PWR_CR10_RETRBSEN_STANDBY_VBAT 1U |
| 108 | #define PWR_CR10_RETRBSEN_STANDBY 2U |
| 109 | |
| 110 | /* PWR_CR11 register fields */ |
| 111 | #define PWR_CR11_DDRRETDIS BIT(0) |
| 112 | |
| 113 | /* PWR_BDCR register fields */ |
| 114 | #define PWR_BDCR_DBP BIT(0) |
| 115 | |
| 116 | /* PWR_CPU1CR register fields */ |
| 117 | #define PWR_CPU1CR_PDDS_D2 BIT(0) |
| 118 | #define PWR_CPU1CR_PDDS_D1 BIT(1) |
| 119 | #define PWR_CPU1CR_VBF BIT(4) |
| 120 | #define PWR_CPU1CR_STOPF BIT(5) |
| 121 | #define PWR_CPU1CR_SBF BIT(6) |
| 122 | #define PWR_CPU1CR_SBF_D1 BIT(7) |
| 123 | #define PWR_CPU1CR_CSSF BIT(9) |
| 124 | #define PWR_CPU1CR_STANDBYWFIL2 BIT(15) |
| 125 | #define PWR_CPU1CR_LPDS_D1 BIT(16) |
| 126 | #define PWR_CPU1CR_LVDS_D1 BIT(17) |
| 127 | |
| 128 | /* PWR_CPU2CR register fields */ |
| 129 | #define PWR_CPU2CR_PDDS_D2 BIT(0) |
| 130 | #define PWR_CPU2CR_VBF BIT(4) |
| 131 | #define PWR_CPU2CR_STOPF BIT(5) |
| 132 | #define PWR_CPU2CR_SBF BIT(6) |
| 133 | #define PWR_CPU2CR_SBF_D2 BIT(7) |
| 134 | #define PWR_CPU2CR_CSSF BIT(9) |
| 135 | #define PWR_CPU2CR_DEEPSLEEP BIT(15) |
| 136 | #define PWR_CPU2CR_LPDS_D2 BIT(16) |
| 137 | #define PWR_CPU2CR_LVDS_D2 BIT(17) |
| 138 | |
| 139 | /* PWR_D1CR register fields */ |
| 140 | #define PWR_D1CR_LPCFG_D1 BIT(0) |
| 141 | #define PWR_D1CR_POPL_D1_MASK GENMASK_32(12, 8) |
| 142 | #define PWR_D1CR_POPL_D1_SHIFT 8 |
| 143 | |
| 144 | /* PWR_D2CR register fields */ |
| 145 | #define PWR_D2CR_LPCFG_D2 BIT(0) |
| 146 | #define PWR_D2CR_POPL_D2_MASK GENMASK_32(12, 8) |
| 147 | #define PWR_D2CR_POPL_D2_SHIFT 8 |
| 148 | #define PWR_D2CR_LPLVDLY_D2_MASK GENMASK_32(18, 16) |
| 149 | #define PWR_D2CR_LPLVDLY_D2_SHIFT 16 |
| 150 | #define PWR_D2CR_PODH_D2_MASK GENMASK_32(27, 24) |
| 151 | #define PWR_D2CR_PODH_D2_SHIFT 24 |
| 152 | |
| 153 | /* PWR_WKUPCR1 register fields */ |
| 154 | #define PWR_WKUPCR1_WKUPC BIT(0) |
| 155 | #define PWR_WKUPCR1_WKUPP BIT(8) |
| 156 | #define PWR_WKUPCR1_WKUPPUPD_MASK GENMASK_32(13, 12) |
| 157 | #define PWR_WKUPCR1_WKUPPUPD_SHIFT 12 |
| 158 | #define PWR_WKUPCR1_WKUPENCPU1 BIT(16) |
| 159 | #define PWR_WKUPCR1_WKUPENCPU2 BIT(17) |
| 160 | #define PWR_WKUPCR1_WKUPF BIT(31) |
| 161 | |
| 162 | /* PWR_WKUPCR2 register fields */ |
| 163 | #define PWR_WKUPCR2_WKUPC BIT(0) |
| 164 | #define PWR_WKUPCR2_WKUPP BIT(8) |
| 165 | #define PWR_WKUPCR2_WKUPPUPD_MASK GENMASK_32(13, 12) |
| 166 | #define PWR_WKUPCR2_WKUPPUPD_SHIFT 12 |
| 167 | #define PWR_WKUPCR2_WKUPENCPU1 BIT(16) |
| 168 | #define PWR_WKUPCR2_WKUPENCPU2 BIT(17) |
| 169 | #define PWR_WKUPCR2_WKUPF BIT(31) |
| 170 | |
| 171 | /* PWR_WKUPCR3 register fields */ |
| 172 | #define PWR_WKUPCR3_WKUPC BIT(0) |
| 173 | #define PWR_WKUPCR3_WKUPP BIT(8) |
| 174 | #define PWR_WKUPCR3_WKUPPUPD_MASK GENMASK_32(13, 12) |
| 175 | #define PWR_WKUPCR3_WKUPPUPD_SHIFT 12 |
| 176 | #define PWR_WKUPCR3_WKUPENCPU1 BIT(16) |
| 177 | #define PWR_WKUPCR3_WKUPENCPU2 BIT(17) |
| 178 | #define PWR_WKUPCR3_WKUPF BIT(31) |
| 179 | |
| 180 | /* PWR_WKUPCR4 register fields */ |
| 181 | #define PWR_WKUPCR4_WKUPC BIT(0) |
| 182 | #define PWR_WKUPCR4_WKUPP BIT(8) |
| 183 | #define PWR_WKUPCR4_WKUPPUPD_MASK GENMASK_32(13, 12) |
| 184 | #define PWR_WKUPCR4_WKUPPUPD_SHIFT 12 |
| 185 | #define PWR_WKUPCR4_WKUPENCPU1 BIT(16) |
| 186 | #define PWR_WKUPCR4_WKUPENCPU2 BIT(17) |
| 187 | #define PWR_WKUPCR4_WKUPF BIT(31) |
| 188 | |
| 189 | /* PWR_WKUPCR5 register fields */ |
| 190 | #define PWR_WKUPCR5_WKUPC BIT(0) |
| 191 | #define PWR_WKUPCR5_WKUPP BIT(8) |
| 192 | #define PWR_WKUPCR5_WKUPPUPD_MASK GENMASK_32(13, 12) |
| 193 | #define PWR_WKUPCR5_WKUPPUPD_SHIFT 12 |
| 194 | #define PWR_WKUPCR5_WKUPENCPU1 BIT(16) |
| 195 | #define PWR_WKUPCR5_WKUPENCPU2 BIT(17) |
| 196 | #define PWR_WKUPCR5_WKUPF BIT(31) |
| 197 | |
| 198 | /* PWR_WKUPCR6 register fields */ |
| 199 | #define PWR_WKUPCR6_WKUPC BIT(0) |
| 200 | #define PWR_WKUPCR6_WKUPP BIT(8) |
| 201 | #define PWR_WKUPCR6_WKUPPUPD_MASK GENMASK_32(13, 12) |
| 202 | #define PWR_WKUPCR6_WKUPPUPD_SHIFT 12 |
| 203 | #define PWR_WKUPCR6_WKUPENCPU1 BIT(16) |
| 204 | #define PWR_WKUPCR6_WKUPENCPU2 BIT(17) |
| 205 | #define PWR_WKUPCR6_WKUPF BIT(31) |
| 206 | |
| 207 | /* PWR_RSECCFGR register fields */ |
| 208 | #define PWR_RSECCFGR_RSEC0 BIT(0) |
| 209 | #define PWR_RSECCFGR_RSEC1 BIT(1) |
| 210 | #define PWR_RSECCFGR_RSEC2 BIT(2) |
| 211 | #define PWR_RSECCFGR_RSEC3 BIT(3) |
| 212 | #define PWR_RSECCFGR_RSEC4 BIT(4) |
| 213 | #define PWR_RSECCFGR_RSEC5 BIT(5) |
| 214 | #define PWR_RSECCFGR_RSEC6 BIT(6) |
| 215 | |
| 216 | /* PWR_RPRIVCFGR register fields */ |
| 217 | #define PWR_RPRIVCFGR_RPRIV0 BIT(0) |
| 218 | #define PWR_RPRIVCFGR_RPRIV1 BIT(1) |
| 219 | #define PWR_RPRIVCFGR_RPRIV2 BIT(2) |
| 220 | #define PWR_RPRIVCFGR_RPRIV3 BIT(3) |
| 221 | #define PWR_RPRIVCFGR_RPRIV4 BIT(4) |
| 222 | #define PWR_RPRIVCFGR_RPRIV5 BIT(5) |
| 223 | #define PWR_RPRIVCFGR_RPRIV6 BIT(6) |
| 224 | |
| 225 | /* PWR_R0CIDCFGR register fields */ |
| 226 | #define PWR_R0CIDCFGR_CFEN BIT(0) |
| 227 | #define PWR_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4) |
| 228 | #define PWR_R0CIDCFGR_SCID_SHIFT 4 |
| 229 | |
| 230 | /* PWR_R1CIDCFGR register fields */ |
| 231 | #define PWR_R1CIDCFGR_CFEN BIT(0) |
| 232 | #define PWR_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4) |
| 233 | #define PWR_R1CIDCFGR_SCID_SHIFT 4 |
| 234 | |
| 235 | /* PWR_R2CIDCFGR register fields */ |
| 236 | #define PWR_R2CIDCFGR_CFEN BIT(0) |
| 237 | #define PWR_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4) |
| 238 | #define PWR_R2CIDCFGR_SCID_SHIFT 4 |
| 239 | |
| 240 | /* PWR_R3CIDCFGR register fields */ |
| 241 | #define PWR_R3CIDCFGR_CFEN BIT(0) |
| 242 | #define PWR_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4) |
| 243 | #define PWR_R3CIDCFGR_SCID_SHIFT 4 |
| 244 | |
| 245 | /* PWR_R4CIDCFGR register fields */ |
| 246 | #define PWR_R4CIDCFGR_CFEN BIT(0) |
| 247 | #define PWR_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4) |
| 248 | #define PWR_R4CIDCFGR_SCID_SHIFT 4 |
| 249 | |
| 250 | /* PWR_R5CIDCFGR register fields */ |
| 251 | #define PWR_R5CIDCFGR_CFEN BIT(0) |
| 252 | #define PWR_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4) |
| 253 | #define PWR_R5CIDCFGR_SCID_SHIFT 4 |
| 254 | |
| 255 | /* PWR_R6CIDCFGR register fields */ |
| 256 | #define PWR_R6CIDCFGR_CFEN BIT(0) |
| 257 | #define PWR_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4) |
| 258 | #define PWR_R6CIDCFGR_SCID_SHIFT 4 |
| 259 | |
| 260 | /* PWR_WIOSECCFGR register fields */ |
| 261 | #define PWR_WIOSECCFGR_WIOSEC1 BIT(0) |
| 262 | #define PWR_WIOSECCFGR_WIOSEC2 BIT(1) |
| 263 | #define PWR_WIOSECCFGR_WIOSEC3 BIT(2) |
| 264 | #define PWR_WIOSECCFGR_WIOSEC4 BIT(3) |
| 265 | #define PWR_WIOSECCFGR_WIOSEC5 BIT(4) |
| 266 | #define PWR_WIOSECCFGR_WIOSEC6 BIT(5) |
| 267 | |
| 268 | /* PWR_WIOPRIVCFGR register fields */ |
| 269 | #define PWR_WIOPRIVCFGR_WIOPRIV1 BIT(0) |
| 270 | #define PWR_WIOPRIVCFGR_WIOPRIV2 BIT(1) |
| 271 | #define PWR_WIOPRIVCFGR_WIOPRIV3 BIT(2) |
| 272 | #define PWR_WIOPRIVCFGR_WIOPRIV4 BIT(3) |
| 273 | #define PWR_WIOPRIVCFGR_WIOPRIV5 BIT(4) |
| 274 | #define PWR_WIOPRIVCFGR_WIOPRIV6 BIT(5) |
| 275 | |
| 276 | /* PWR_WIO1CIDCFGR register fields */ |
| 277 | #define PWR_WIO1CIDCFGR_CFEN BIT(0) |
| 278 | #define PWR_WIO1CIDCFGR_SEM_EN BIT(1) |
| 279 | #define PWR_WIO1CIDCFGR_SCID_MASK GENMASK_32(6, 4) |
| 280 | #define PWR_WIO1CIDCFGR_SCID_SHIFT 4 |
| 281 | #define PWR_WIO1CIDCFGR_SEMWLC0 BIT(16) |
| 282 | #define PWR_WIO1CIDCFGR_SEMWLC1 BIT(17) |
| 283 | #define PWR_WIO1CIDCFGR_SEMWLC2 BIT(18) |
| 284 | #define PWR_WIO1CIDCFGR_SEMWLC3 BIT(19) |
| 285 | #define PWR_WIO1CIDCFGR_SEMWLC4 BIT(20) |
| 286 | #define PWR_WIO1CIDCFGR_SEMWLC5 BIT(21) |
| 287 | #define PWR_WIO1CIDCFGR_SEMWLC6 BIT(22) |
| 288 | #define PWR_WIO1CIDCFGR_SEMWLC7 BIT(23) |
| 289 | |
| 290 | /* PWR_WIO1SEMCR register fields */ |
| 291 | #define PWR_WIO1SEMCR_SEM_MUTEX BIT(0) |
| 292 | #define PWR_WIO1SEMCR_SEMCID_MASK GENMASK_32(6, 4) |
| 293 | #define PWR_WIO1SEMCR_SEMCID_SHIFT 4 |
| 294 | |
| 295 | /* PWR_WIO2CIDCFGR register fields */ |
| 296 | #define PWR_WIO2CIDCFGR_CFEN BIT(0) |
| 297 | #define PWR_WIO2CIDCFGR_SEM_EN BIT(1) |
| 298 | #define PWR_WIO2CIDCFGR_SCID_MASK GENMASK_32(6, 4) |
| 299 | #define PWR_WIO2CIDCFGR_SCID_SHIFT 4 |
| 300 | #define PWR_WIO2CIDCFGR_SEMWLC0 BIT(16) |
| 301 | #define PWR_WIO2CIDCFGR_SEMWLC1 BIT(17) |
| 302 | #define PWR_WIO2CIDCFGR_SEMWLC2 BIT(18) |
| 303 | #define PWR_WIO2CIDCFGR_SEMWLC3 BIT(19) |
| 304 | #define PWR_WIO2CIDCFGR_SEMWLC4 BIT(20) |
| 305 | #define PWR_WIO2CIDCFGR_SEMWLC5 BIT(21) |
| 306 | #define PWR_WIO2CIDCFGR_SEMWLC6 BIT(22) |
| 307 | #define PWR_WIO2CIDCFGR_SEMWLC7 BIT(23) |
| 308 | |
| 309 | /* PWR_WIO2SEMCR register fields */ |
| 310 | #define PWR_WIO2SEMCR_SEM_MUTEX BIT(0) |
| 311 | #define PWR_WIO2SEMCR_SEMCID_MASK GENMASK_32(6, 4) |
| 312 | #define PWR_WIO2SEMCR_SEMCID_SHIFT 4 |
| 313 | |
| 314 | /* PWR_WIO3CIDCFGR register fields */ |
| 315 | #define PWR_WIO3CIDCFGR_CFEN BIT(0) |
| 316 | #define PWR_WIO3CIDCFGR_SEM_EN BIT(1) |
| 317 | #define PWR_WIO3CIDCFGR_SCID_MASK GENMASK_32(6, 4) |
| 318 | #define PWR_WIO3CIDCFGR_SCID_SHIFT 4 |
| 319 | #define PWR_WIO3CIDCFGR_SEMWLC0 BIT(16) |
| 320 | #define PWR_WIO3CIDCFGR_SEMWLC1 BIT(17) |
| 321 | #define PWR_WIO3CIDCFGR_SEMWLC2 BIT(18) |
| 322 | #define PWR_WIO3CIDCFGR_SEMWLC3 BIT(19) |
| 323 | #define PWR_WIO3CIDCFGR_SEMWLC4 BIT(20) |
| 324 | #define PWR_WIO3CIDCFGR_SEMWLC5 BIT(21) |
| 325 | #define PWR_WIO3CIDCFGR_SEMWLC6 BIT(22) |
| 326 | #define PWR_WIO3CIDCFGR_SEMWLC7 BIT(23) |
| 327 | |
| 328 | /* PWR_WIO3SEMCR register fields */ |
| 329 | #define PWR_WIO3SEMCR_SEM_MUTEX BIT(0) |
| 330 | #define PWR_WIO3SEMCR_SEMCID_MASK GENMASK_32(6, 4) |
| 331 | #define PWR_WIO3SEMCR_SEMCID_SHIFT 4 |
| 332 | |
| 333 | /* PWR_WIO4CIDCFGR register fields */ |
| 334 | #define PWR_WIO4CIDCFGR_CFEN BIT(0) |
| 335 | #define PWR_WIO4CIDCFGR_SEM_EN BIT(1) |
| 336 | #define PWR_WIO4CIDCFGR_SCID_MASK GENMASK_32(6, 4) |
| 337 | #define PWR_WIO4CIDCFGR_SCID_SHIFT 4 |
| 338 | #define PWR_WIO4CIDCFGR_SEMWLC0 BIT(16) |
| 339 | #define PWR_WIO4CIDCFGR_SEMWLC1 BIT(17) |
| 340 | #define PWR_WIO4CIDCFGR_SEMWLC2 BIT(18) |
| 341 | #define PWR_WIO4CIDCFGR_SEMWLC3 BIT(19) |
| 342 | #define PWR_WIO4CIDCFGR_SEMWLC4 BIT(20) |
| 343 | #define PWR_WIO4CIDCFGR_SEMWLC5 BIT(21) |
| 344 | #define PWR_WIO4CIDCFGR_SEMWLC6 BIT(22) |
| 345 | #define PWR_WIO4CIDCFGR_SEMWLC7 BIT(23) |
| 346 | |
| 347 | /* PWR_WIO4SEMCR register fields */ |
| 348 | #define PWR_WIO4SEMCR_SEM_MUTEX BIT(0) |
| 349 | #define PWR_WIO4SEMCR_SEMCID_MASK GENMASK_32(6, 4) |
| 350 | #define PWR_WIO4SEMCR_SEMCID_SHIFT 4 |
| 351 | |
| 352 | /* PWR_WIO5CIDCFGR register fields */ |
| 353 | #define PWR_WIO5CIDCFGR_CFEN BIT(0) |
| 354 | #define PWR_WIO5CIDCFGR_SEM_EN BIT(1) |
| 355 | #define PWR_WIO5CIDCFGR_SCID_MASK GENMASK_32(6, 4) |
| 356 | #define PWR_WIO5CIDCFGR_SCID_SHIFT 4 |
| 357 | #define PWR_WIO5CIDCFGR_SEMWLC0 BIT(16) |
| 358 | #define PWR_WIO5CIDCFGR_SEMWLC1 BIT(17) |
| 359 | #define PWR_WIO5CIDCFGR_SEMWLC2 BIT(18) |
| 360 | #define PWR_WIO5CIDCFGR_SEMWLC3 BIT(19) |
| 361 | #define PWR_WIO5CIDCFGR_SEMWLC4 BIT(20) |
| 362 | #define PWR_WIO5CIDCFGR_SEMWLC5 BIT(21) |
| 363 | #define PWR_WIO5CIDCFGR_SEMWLC6 BIT(22) |
| 364 | #define PWR_WIO5CIDCFGR_SEMWLC7 BIT(23) |
| 365 | |
| 366 | /* PWR_WIO5SEMCR register fields */ |
| 367 | #define PWR_WIO5SEMCR_SEM_MUTEX BIT(0) |
| 368 | #define PWR_WIO5SEMCR_SEMCID_MASK GENMASK_32(6, 4) |
| 369 | #define PWR_WIO5SEMCR_SEMCID_SHIFT 4 |
| 370 | |
| 371 | /* PWR_WIO6CIDCFGR register fields */ |
| 372 | #define PWR_WIO6CIDCFGR_CFEN BIT(0) |
| 373 | #define PWR_WIO6CIDCFGR_SEM_EN BIT(1) |
| 374 | #define PWR_WIO6CIDCFGR_SCID_MASK GENMASK_32(6, 4) |
| 375 | #define PWR_WIO6CIDCFGR_SCID_SHIFT 4 |
| 376 | #define PWR_WIO6CIDCFGR_SEMWLC0 BIT(16) |
| 377 | #define PWR_WIO6CIDCFGR_SEMWLC1 BIT(17) |
| 378 | #define PWR_WIO6CIDCFGR_SEMWLC2 BIT(18) |
| 379 | #define PWR_WIO6CIDCFGR_SEMWLC3 BIT(19) |
| 380 | #define PWR_WIO6CIDCFGR_SEMWLC4 BIT(20) |
| 381 | #define PWR_WIO6CIDCFGR_SEMWLC5 BIT(21) |
| 382 | #define PWR_WIO6CIDCFGR_SEMWLC6 BIT(22) |
| 383 | #define PWR_WIO6CIDCFGR_SEMWLC7 BIT(23) |
| 384 | |
| 385 | /* PWR_WIO6SEMCR register fields */ |
| 386 | #define PWR_WIO6SEMCR_SEM_MUTEX BIT(0) |
| 387 | #define PWR_WIO6SEMCR_SEMCID_MASK GENMASK_32(6, 4) |
| 388 | #define PWR_WIO6SEMCR_SEMCID_SHIFT 4 |
| 389 | |
| 390 | /* PWR_CPU1D1SR register fields */ |
| 391 | #define PWR_CPU1D1SR_HOLD_BOOT BIT(0) |
| 392 | #define PWR_CPU1D1SR_CSTATE_MASK GENMASK_32(3, 2) |
| 393 | #define PWR_CPU1D1SR_CSTATE_SHIFT 2 |
| 394 | #define PWR_CPU1D1SR_DSTATE_MASK GENMASK_32(10, 8) |
| 395 | #define PWR_CPU1D1SR_DSTATE_SHIFT 8 |
| 396 | |
| 397 | /* PWR_CPU2D2SR register fields */ |
| 398 | #define PWR_CPU2D2SR_HOLD_BOOT BIT(0) |
| 399 | #define PWR_CPU2D2SR_WFBEN BIT(1) |
| 400 | #define PWR_CPU2D2SR_CSTATE_MASK GENMASK_32(3, 2) |
| 401 | #define PWR_CPU2D2SR_CSTATE_SHIFT 2 |
| 402 | #define PWR_CPU2D2SR_DSTATE_MASK GENMASK_32(10, 8) |
| 403 | #define PWR_CPU2D2SR_DSTATE_SHIFT 8 |
| 404 | |
| 405 | /* PWR_DBGR register fields */ |
| 406 | #define PWR_DBGR_VDDIOKRETRAM BIT(16) |
| 407 | #define PWR_DBGR_VDDIOKBKPRAM BIT(17) |
| 408 | |
| 409 | /* PWR_VERR register fields */ |
| 410 | #define PWR_VERR_MINREV_MASK GENMASK_32(3, 0) |
| 411 | #define PWR_VERR_MINREV_SHIFT 0 |
| 412 | #define PWR_VERR_MAJREV_MASK GENMASK_32(7, 4) |
| 413 | #define PWR_VERR_MAJREV_SHIFT 4 |
| 414 | |
| 415 | #endif /* STM32MP21_PWR_H */ |
| 416 | |