blob: 90987020632fd8b26060edb0c0dd10579f4a3f02 [file] [log] [blame]
Andre Przywaraaa26f532017-12-08 01:27:02 +00001#
2# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/xlat_tables_v2/xlat_tables.mk
8
9AW_PLAT := plat/allwinner
Icenowy Zheng8d769822018-07-22 21:30:14 +080010AW_DRIVERS := drivers/allwinner
Andre Przywaraaa26f532017-12-08 01:27:02 +000011
12PLAT_INCLUDES := -Iinclude/plat/arm/common \
13 -Iinclude/plat/arm/common/aarch64 \
14 -I${AW_PLAT}/common/include \
15 -I${AW_PLAT}/${PLAT}/include
16
17PLAT_BL_COMMON_SOURCES := drivers/console/${ARCH}/console.S \
Andre Przywaraeeeba252018-09-09 01:39:57 +010018 drivers/mentor/i2c/mi2cv.c \
Andre Przywaraaa26f532017-12-08 01:27:02 +000019 drivers/ti/uart/${ARCH}/16550_console.S \
20 ${XLAT_TABLES_LIB_SRCS} \
21 ${AW_PLAT}/common/plat_helpers.S \
22 ${AW_PLAT}/common/sunxi_common.c
23
24BL31_SOURCES += drivers/arm/gic/common/gic_common.c \
25 drivers/arm/gic/v2/gicv2_helpers.c \
26 drivers/arm/gic/v2/gicv2_main.c \
27 drivers/delay_timer/delay_timer.c \
28 drivers/delay_timer/generic_delay_timer.c \
29 lib/cpus/${ARCH}/cortex_a53.S \
30 plat/common/plat_gicv2.c \
31 plat/common/plat_psci_common.c \
32 ${AW_PLAT}/common/sunxi_bl31_setup.c \
33 ${AW_PLAT}/common/sunxi_cpu_ops.c \
34 ${AW_PLAT}/common/sunxi_pm.c \
Icenowy Zheng7508bef2018-07-21 20:41:12 +080035 ${AW_PLAT}/sun50i_h6/sunxi_power.c \
Andre Przywaraaa26f532017-12-08 01:27:02 +000036 ${AW_PLAT}/common/sunxi_security.c \
37 ${AW_PLAT}/common/sunxi_topology.c
38
39# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
40COLD_BOOT_SINGLE_CPU := 1
41
42# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
43ERRATA_A53_835769 := 1
44ERRATA_A53_843419 := 1
45ERRATA_A53_855873 := 1
46
47# Disable the PSCI platform compatibility layer.
48ENABLE_PLAT_COMPAT := 0
49
50MULTI_CONSOLE_API := 1
51
52# Prohibit using deprecated interfaces. We rely on this for this platform.
53ERROR_DEPRECATED := 1
54
55# The reset vector can be changed for each CPU.
56PROGRAMMABLE_RESET_ADDRESS := 1
57
58# Allow mapping read-only data as execute-never.
59SEPARATE_CODE_AND_RODATA := 1
60
61# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
62RESET_TO_BL31 := 1