Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __PLATFORM_H__ |
| 32 | #define __PLATFORM_H__ |
| 33 | |
| 34 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 35 | |
| 36 | |
| 37 | /******************************************************************************* |
| 38 | * Platform binary types for linking |
| 39 | ******************************************************************************/ |
| 40 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 41 | #define PLATFORM_LINKER_ARCH aarch64 |
| 42 | |
| 43 | /******************************************************************************* |
| 44 | * Generic platform constants |
| 45 | ******************************************************************************/ |
Andrew Thoelke | 65668f9 | 2014-03-20 10:48:23 +0000 | [diff] [blame] | 46 | |
| 47 | /* Size of cacheable stacks */ |
| 48 | #define PLATFORM_STACK_SIZE 0x800 |
| 49 | |
| 50 | /* Size of coherent stacks for debug and release builds */ |
| 51 | #if DEBUG |
| 52 | #define PCPU_DV_MEM_STACK_SIZE 0x400 |
| 53 | #else |
| 54 | #define PCPU_DV_MEM_STACK_SIZE 0x300 |
| 55 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 56 | |
| 57 | #define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r" |
Harry Liebel | 561cd33 | 2014-02-14 14:42:48 +0000 | [diff] [blame] | 58 | |
| 59 | /* Trusted Boot Firmware BL2 */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 60 | #define BL2_IMAGE_NAME "bl2.bin" |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 61 | |
Harry Liebel | 561cd33 | 2014-02-14 14:42:48 +0000 | [diff] [blame] | 62 | /* EL3 Runtime Firmware BL31 */ |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 63 | #define BL31_IMAGE_NAME "bl31.bin" |
| 64 | |
Harry Liebel | 561cd33 | 2014-02-14 14:42:48 +0000 | [diff] [blame] | 65 | /* Secure Payload BL32 (Trusted OS) */ |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 66 | #define BL32_IMAGE_NAME "bl32.bin" |
| 67 | |
Harry Liebel | 561cd33 | 2014-02-14 14:42:48 +0000 | [diff] [blame] | 68 | /* Non-Trusted Firmware BL33 and its load address */ |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 69 | #define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */ |
| 70 | #define NS_IMAGE_OFFSET (DRAM_BASE + 0x8000000) /* DRAM + 128MB */ |
| 71 | |
Harry Liebel | 561cd33 | 2014-02-14 14:42:48 +0000 | [diff] [blame] | 72 | /* Firmware Image Package */ |
| 73 | #define FIP_IMAGE_NAME "fip.bin" |
| 74 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 75 | #define PLATFORM_CACHE_LINE_SIZE 64 |
| 76 | #define PLATFORM_CLUSTER_COUNT 2ull |
| 77 | #define PLATFORM_CLUSTER0_CORE_COUNT 4 |
| 78 | #define PLATFORM_CLUSTER1_CORE_COUNT 4 |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 79 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ |
| 80 | PLATFORM_CLUSTER0_CORE_COUNT) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 81 | #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 |
| 82 | #define PRIMARY_CPU 0x0 |
Harry Liebel | 561cd33 | 2014-02-14 14:42:48 +0000 | [diff] [blame] | 83 | #define MAX_IO_DEVICES 3 |
James Morrissey | f2f9bb5 | 2014-02-10 16:18:59 +0000 | [diff] [blame] | 84 | #define MAX_IO_HANDLES 4 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 85 | |
| 86 | /* Constants for accessing platform configuration */ |
| 87 | #define CONFIG_GICD_ADDR 0 |
| 88 | #define CONFIG_GICC_ADDR 1 |
| 89 | #define CONFIG_GICH_ADDR 2 |
| 90 | #define CONFIG_GICV_ADDR 3 |
| 91 | #define CONFIG_MAX_AFF0 4 |
| 92 | #define CONFIG_MAX_AFF1 5 |
| 93 | /* Indicate whether the CPUECTLR SMP bit should be enabled. */ |
| 94 | #define CONFIG_CPU_SETUP 6 |
| 95 | #define CONFIG_BASE_MMAP 7 |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 96 | /* Indicates whether CCI should be enabled on the platform. */ |
| 97 | #define CONFIG_HAS_CCI 8 |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 98 | #define CONFIG_HAS_TZC 9 |
| 99 | #define CONFIG_LIMIT 10 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 100 | |
| 101 | /******************************************************************************* |
| 102 | * Platform memory map related constants |
| 103 | ******************************************************************************/ |
| 104 | #define TZROM_BASE 0x00000000 |
| 105 | #define TZROM_SIZE 0x04000000 |
| 106 | |
| 107 | #define TZRAM_BASE 0x04000000 |
| 108 | #define TZRAM_SIZE 0x40000 |
| 109 | |
| 110 | #define FLASH0_BASE 0x08000000 |
| 111 | #define FLASH0_SIZE TZROM_SIZE |
| 112 | |
| 113 | #define FLASH1_BASE 0x0c000000 |
| 114 | #define FLASH1_SIZE 0x04000000 |
| 115 | |
| 116 | #define PSRAM_BASE 0x14000000 |
| 117 | #define PSRAM_SIZE 0x04000000 |
| 118 | |
| 119 | #define VRAM_BASE 0x18000000 |
| 120 | #define VRAM_SIZE 0x02000000 |
| 121 | |
| 122 | /* Aggregate of all devices in the first GB */ |
| 123 | #define DEVICE0_BASE 0x1a000000 |
| 124 | #define DEVICE0_SIZE 0x12200000 |
| 125 | |
| 126 | #define DEVICE1_BASE 0x2f000000 |
| 127 | #define DEVICE1_SIZE 0x200000 |
| 128 | |
| 129 | #define NSRAM_BASE 0x2e000000 |
| 130 | #define NSRAM_SIZE 0x10000 |
| 131 | |
| 132 | /* Location of trusted dram on the base fvp */ |
| 133 | #define TZDRAM_BASE 0x06000000 |
| 134 | #define TZDRAM_SIZE 0x02000000 |
| 135 | #define MBOX_OFF 0x1000 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 136 | |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 137 | /* Base address where parameters to BL31 are stored */ |
| 138 | #define PARAMS_BASE TZDRAM_BASE |
| 139 | |
| 140 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 141 | #define DRAM_BASE 0x80000000ull |
| 142 | #define DRAM_SIZE 0x80000000ull |
| 143 | |
| 144 | #define PCIE_EXP_BASE 0x40000000 |
| 145 | #define TZRNG_BASE 0x7fe60000 |
| 146 | #define TZNVCTR_BASE 0x7fe70000 |
| 147 | #define TZROOTKEY_BASE 0x7fe80000 |
| 148 | |
| 149 | /* Memory mapped Generic timer interfaces */ |
| 150 | #define SYS_CNTCTL_BASE 0x2a430000 |
| 151 | #define SYS_CNTREAD_BASE 0x2a800000 |
| 152 | #define SYS_TIMCTL_BASE 0x2a810000 |
| 153 | |
| 154 | /* Counter timer module offsets */ |
| 155 | #define CNTNSAR 0x4 |
| 156 | #define CNTNSAR_NS_SHIFT(x) x |
| 157 | |
| 158 | #define CNTACR_BASE(x) (0x40 + (x << 2)) |
| 159 | #define CNTACR_RPCT_SHIFT 0x0 |
| 160 | #define CNTACR_RVCT_SHIFT 0x1 |
| 161 | #define CNTACR_RFRQ_SHIFT 0x2 |
| 162 | #define CNTACR_RVOFF_SHIFT 0x3 |
| 163 | #define CNTACR_RWVT_SHIFT 0x4 |
| 164 | #define CNTACR_RWPT_SHIFT 0x5 |
| 165 | |
| 166 | /* V2M motherboard system registers & offsets */ |
| 167 | #define VE_SYSREGS_BASE 0x1c010000 |
| 168 | #define V2M_SYS_ID 0x0 |
| 169 | #define V2M_SYS_LED 0x8 |
| 170 | #define V2M_SYS_CFGDATA 0xa0 |
| 171 | #define V2M_SYS_CFGCTRL 0xa4 |
| 172 | |
| 173 | /* |
| 174 | * V2M sysled bit definitions. The values written to this |
| 175 | * register are defined in arch.h & runtime_svc.h. Only |
| 176 | * used by the primary cpu to diagnose any cold boot issues. |
| 177 | * |
| 178 | * SYS_LED[0] - Security state (S=0/NS=1) |
| 179 | * SYS_LED[2:1] - Exception Level (EL3-EL0) |
| 180 | * SYS_LED[7:3] - Exception Class (Sync/Async & origin) |
| 181 | * |
| 182 | */ |
| 183 | #define SYS_LED_SS_SHIFT 0x0 |
| 184 | #define SYS_LED_EL_SHIFT 0x1 |
| 185 | #define SYS_LED_EC_SHIFT 0x3 |
| 186 | |
| 187 | #define SYS_LED_SS_MASK 0x1 |
| 188 | #define SYS_LED_EL_MASK 0x3 |
| 189 | #define SYS_LED_EC_MASK 0x1f |
| 190 | |
| 191 | /* V2M sysid register bits */ |
| 192 | #define SYS_ID_REV_SHIFT 27 |
| 193 | #define SYS_ID_HBI_SHIFT 16 |
| 194 | #define SYS_ID_BLD_SHIFT 12 |
| 195 | #define SYS_ID_ARCH_SHIFT 8 |
| 196 | #define SYS_ID_FPGA_SHIFT 0 |
| 197 | |
| 198 | #define SYS_ID_REV_MASK 0xf |
| 199 | #define SYS_ID_HBI_MASK 0xfff |
| 200 | #define SYS_ID_BLD_MASK 0xf |
| 201 | #define SYS_ID_ARCH_MASK 0xf |
| 202 | #define SYS_ID_FPGA_MASK 0xff |
| 203 | |
| 204 | #define SYS_ID_BLD_LENGTH 4 |
| 205 | |
| 206 | #define REV_FVP 0x0 |
| 207 | #define HBI_FVP_BASE 0x020 |
| 208 | #define HBI_FOUNDATION 0x010 |
| 209 | |
| 210 | #define BLD_GIC_VE_MMAP 0x0 |
| 211 | #define BLD_GIC_A53A57_MMAP 0x1 |
| 212 | |
| 213 | #define ARCH_MODEL 0x1 |
| 214 | |
| 215 | /* FVP Power controller base address*/ |
| 216 | #define PWRC_BASE 0x1c100000 |
| 217 | |
| 218 | /******************************************************************************* |
| 219 | * Platform specific per affinity states. Distinction between off and suspend |
| 220 | * is made to allow reporting of a suspended cpu as still being on e.g. in the |
| 221 | * affinity_info psci call. |
| 222 | ******************************************************************************/ |
| 223 | #define PLATFORM_MAX_AFF0 4 |
| 224 | #define PLATFORM_MAX_AFF1 2 |
| 225 | #define PLAT_AFF_UNK 0xff |
| 226 | |
| 227 | #define PLAT_AFF0_OFF 0x0 |
| 228 | #define PLAT_AFF0_ONPENDING 0x1 |
| 229 | #define PLAT_AFF0_SUSPEND 0x2 |
| 230 | #define PLAT_AFF0_ON 0x3 |
| 231 | |
| 232 | #define PLAT_AFF1_OFF 0x0 |
| 233 | #define PLAT_AFF1_ONPENDING 0x1 |
| 234 | #define PLAT_AFF1_SUSPEND 0x2 |
| 235 | #define PLAT_AFF1_ON 0x3 |
| 236 | |
| 237 | /******************************************************************************* |
| 238 | * BL2 specific defines. |
| 239 | ******************************************************************************/ |
Jeenu Viswambharan | 74cbb83 | 2014-02-17 17:26:51 +0000 | [diff] [blame] | 240 | #define BL2_BASE 0x0402D000 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 241 | |
| 242 | /******************************************************************************* |
| 243 | * BL31 specific defines. |
| 244 | ******************************************************************************/ |
Jeenu Viswambharan | 74cbb83 | 2014-02-17 17:26:51 +0000 | [diff] [blame] | 245 | #define BL31_BASE 0x0400C000 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 246 | |
| 247 | /******************************************************************************* |
Achin Gupta | a3050ed | 2014-02-19 17:52:35 +0000 | [diff] [blame] | 248 | * BL32 specific defines. |
| 249 | ******************************************************************************/ |
| 250 | #define BL32_BASE (TZDRAM_BASE + 0x2000) |
| 251 | |
| 252 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 253 | * Platform specific page table and MMU setup constants |
| 254 | ******************************************************************************/ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 255 | #define ADDR_SPACE_SIZE (1ull << 32) |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 256 | #define MAX_XLAT_TABLES 3 |
| 257 | #define MAX_MMAP_REGIONS 16 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 258 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 259 | |
| 260 | /******************************************************************************* |
| 261 | * CCI-400 related constants |
| 262 | ******************************************************************************/ |
| 263 | #define CCI400_BASE 0x2c090000 |
| 264 | #define CCI400_SL_IFACE_CLUSTER0 3 |
| 265 | #define CCI400_SL_IFACE_CLUSTER1 4 |
| 266 | #define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \ |
| 267 | CCI400_SL_IFACE_CLUSTER1 : \ |
| 268 | CCI400_SL_IFACE_CLUSTER0) |
| 269 | |
| 270 | /******************************************************************************* |
| 271 | * GIC-400 & interrupt handling related constants |
| 272 | ******************************************************************************/ |
| 273 | /* VE compatible GIC memory map */ |
| 274 | #define VE_GICD_BASE 0x2c001000 |
| 275 | #define VE_GICC_BASE 0x2c002000 |
| 276 | #define VE_GICH_BASE 0x2c004000 |
| 277 | #define VE_GICV_BASE 0x2c006000 |
| 278 | |
| 279 | /* Base FVP compatible GIC memory map */ |
| 280 | #define BASE_GICD_BASE 0x2f000000 |
| 281 | #define BASE_GICR_BASE 0x2f100000 |
| 282 | #define BASE_GICC_BASE 0x2c000000 |
| 283 | #define BASE_GICH_BASE 0x2c010000 |
| 284 | #define BASE_GICV_BASE 0x2c02f000 |
| 285 | |
| 286 | #define IRQ_TZ_WDOG 56 |
| 287 | #define IRQ_SEC_PHY_TIMER 29 |
| 288 | #define IRQ_SEC_SGI_0 8 |
| 289 | #define IRQ_SEC_SGI_1 9 |
| 290 | #define IRQ_SEC_SGI_2 10 |
| 291 | #define IRQ_SEC_SGI_3 11 |
| 292 | #define IRQ_SEC_SGI_4 12 |
| 293 | #define IRQ_SEC_SGI_5 13 |
| 294 | #define IRQ_SEC_SGI_6 14 |
| 295 | #define IRQ_SEC_SGI_7 15 |
| 296 | #define IRQ_SEC_SGI_8 16 |
| 297 | |
| 298 | /******************************************************************************* |
| 299 | * PL011 related constants |
| 300 | ******************************************************************************/ |
Achin Gupta | 8aa0cd4 | 2014-02-09 13:47:08 +0000 | [diff] [blame] | 301 | #define PL011_UART0_BASE 0x1c090000 |
| 302 | #define PL011_UART1_BASE 0x1c0a0000 |
| 303 | #define PL011_UART2_BASE 0x1c0b0000 |
| 304 | #define PL011_UART3_BASE 0x1c0c0000 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 305 | |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 306 | |
| 307 | /******************************************************************************* |
| 308 | * TrustZone address space controller related constants |
| 309 | ******************************************************************************/ |
| 310 | #define TZC400_BASE 0x2a4a0000 |
| 311 | |
| 312 | /* |
| 313 | * The NSAIDs for this platform as used to program the TZC400. |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 314 | */ |
| 315 | |
| 316 | /* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */ |
| 317 | #define FVP_AID_WIDTH 4 |
Andrew Thoelke | fe3374b | 2014-05-09 15:36:13 +0100 | [diff] [blame] | 318 | |
| 319 | /* NSAIDs used by devices in TZC filter 0 on FVP */ |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 320 | #define FVP_NSAID_DEFAULT 0 |
Andrew Thoelke | fe3374b | 2014-05-09 15:36:13 +0100 | [diff] [blame] | 321 | #define FVP_NSAID_PCI 1 |
| 322 | #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 323 | #define FVP_NSAID_AP 9 /* Application Processors */ |
Andrew Thoelke | fe3374b | 2014-05-09 15:36:13 +0100 | [diff] [blame] | 324 | #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 325 | |
Andrew Thoelke | fe3374b | 2014-05-09 15:36:13 +0100 | [diff] [blame] | 326 | /* NSAIDs used by devices in TZC filter 2 on FVP */ |
| 327 | #define FVP_NSAID_HDLCD0 2 |
| 328 | #define FVP_NSAID_CLCD 7 |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 329 | |
| 330 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 331 | /******************************************************************************* |
| 332 | * Declarations and constants to access the mailboxes safely. Each mailbox is |
| 333 | * aligned on the biggest cache line size in the platform. This is known only |
| 334 | * to the platform as it might have a combination of integrated and external |
| 335 | * caches. Such alignment ensures that two maiboxes do not sit on the same cache |
| 336 | * line at any cache level. They could belong to different cpus/clusters & |
| 337 | * get written while being protected by different locks causing corruption of |
| 338 | * a valid mailbox address. |
| 339 | ******************************************************************************/ |
| 340 | #define CACHE_WRITEBACK_SHIFT 6 |
| 341 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 342 | |
| 343 | #ifndef __ASSEMBLY__ |
| 344 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 345 | #include <stdint.h> |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 346 | #include <bl_common.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 347 | |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 348 | typedef volatile struct mailbox { |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 349 | unsigned long value |
| 350 | __attribute__((__aligned__(CACHE_WRITEBACK_GRANULE))); |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 351 | } mailbox_t; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 352 | |
| 353 | /******************************************************************************* |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 354 | * Forward declarations |
| 355 | ******************************************************************************/ |
| 356 | struct plat_pm_ops; |
| 357 | struct meminfo; |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 358 | struct bl31_params; |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 359 | struct image_info; |
| 360 | struct entry_point_info; |
| 361 | |
| 362 | |
| 363 | /******************************************************************************* |
| 364 | * This structure represents the superset of information that is passed to |
| 365 | * BL31 e.g. while passing control to it from BL2 which is bl31_params |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame^] | 366 | * and another platform specific params |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 367 | ******************************************************************************/ |
| 368 | typedef struct bl2_to_bl31_params_mem { |
| 369 | struct bl31_params bl31_params; |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 370 | struct image_info bl31_image_info; |
| 371 | struct image_info bl32_image_info; |
| 372 | struct image_info bl33_image_info; |
| 373 | struct entry_point_info bl33_ep_info; |
| 374 | struct entry_point_info bl32_ep_info; |
| 375 | struct entry_point_info bl31_ep_info; |
| 376 | } bl2_to_bl31_params_mem_t; |
| 377 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 378 | |
| 379 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 380 | * Function and variable prototypes |
| 381 | ******************************************************************************/ |
| 382 | extern unsigned long *bl1_normal_ram_base; |
| 383 | extern unsigned long *bl1_normal_ram_len; |
| 384 | extern unsigned long *bl1_normal_ram_limit; |
| 385 | extern unsigned long *bl1_normal_ram_zi_base; |
| 386 | extern unsigned long *bl1_normal_ram_zi_len; |
| 387 | |
| 388 | extern unsigned long *bl1_coherent_ram_base; |
| 389 | extern unsigned long *bl1_coherent_ram_len; |
| 390 | extern unsigned long *bl1_coherent_ram_limit; |
| 391 | extern unsigned long *bl1_coherent_ram_zi_base; |
| 392 | extern unsigned long *bl1_coherent_ram_zi_len; |
| 393 | extern unsigned long warm_boot_entrypoint; |
| 394 | |
| 395 | extern void bl1_plat_arch_setup(void); |
| 396 | extern void bl2_plat_arch_setup(void); |
| 397 | extern void bl31_plat_arch_setup(void); |
Dan Handley | a4cb68e | 2014-04-23 13:47:06 +0100 | [diff] [blame] | 398 | extern int platform_setup_pm(const struct plat_pm_ops **); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 399 | extern unsigned int platform_get_core_pos(unsigned long mpidr); |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 400 | extern void enable_mmu_el1(void); |
| 401 | extern void enable_mmu_el3(void); |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame^] | 402 | extern void configure_mmu_el1(unsigned long total_base, |
| 403 | unsigned long total_size, |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 404 | unsigned long ro_start, |
| 405 | unsigned long ro_limit, |
| 406 | unsigned long coh_start, |
| 407 | unsigned long coh_limit); |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame^] | 408 | extern void configure_mmu_el3(unsigned long total_base, |
| 409 | unsigned long total_size, |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 410 | unsigned long ro_start, |
| 411 | unsigned long ro_limit, |
| 412 | unsigned long coh_start, |
| 413 | unsigned long coh_limit); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 414 | extern unsigned long platform_get_cfgvar(unsigned int); |
| 415 | extern int platform_config_setup(void); |
| 416 | extern void plat_report_exception(unsigned long); |
| 417 | extern unsigned long plat_get_ns_image_entrypoint(void); |
Achin Gupta | c8afc78 | 2013-11-25 18:45:02 +0000 | [diff] [blame] | 418 | extern unsigned long platform_get_stack(unsigned long mpidr); |
Sandrine Bailleux | 3fa9847 | 2014-03-31 11:25:18 +0100 | [diff] [blame] | 419 | extern uint64_t plat_get_syscnt_freq(void); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 420 | |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 421 | /* Declarations for fvp_gic.c */ |
| 422 | extern void gic_cpuif_deactivate(unsigned int); |
| 423 | extern void gic_cpuif_setup(unsigned int); |
| 424 | extern void gic_pcpu_distif_setup(unsigned int); |
| 425 | extern void gic_setup(void); |
| 426 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 427 | /* Declarations for fvp_topology.c */ |
| 428 | extern int plat_setup_topology(void); |
| 429 | extern int plat_get_max_afflvl(void); |
| 430 | extern unsigned int plat_get_aff_count(unsigned int, unsigned long); |
| 431 | extern unsigned int plat_get_aff_state(unsigned int, unsigned long); |
| 432 | |
James Morrissey | 9d72b4e | 2014-02-10 17:04:32 +0000 | [diff] [blame] | 433 | /* Declarations for plat_io_storage.c */ |
| 434 | extern void io_setup(void); |
| 435 | extern int plat_get_image_source(const char *image_name, |
Dan Handley | a4cb68e | 2014-04-23 13:47:06 +0100 | [diff] [blame] | 436 | uintptr_t *dev_handle, uintptr_t *image_spec); |
James Morrissey | 9d72b4e | 2014-02-10 17:04:32 +0000 | [diff] [blame] | 437 | |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 438 | /* Declarations for plat_security.c */ |
| 439 | extern void plat_security_setup(void); |
| 440 | |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 441 | /* |
| 442 | * Before calling this function BL2 is loaded in memory and its entrypoint |
| 443 | * is set by load_image. This is a placeholder for the platform to change |
| 444 | * the entrypoint of BL2 and set SPSR and security state. |
| 445 | * On FVP we are only setting the security state, entrypoint |
| 446 | */ |
| 447 | extern void bl1_plat_set_bl2_ep_info(struct image_info *image, |
| 448 | struct entry_point_info *ep); |
| 449 | |
| 450 | /* |
| 451 | * Before calling this function BL31 is loaded in memory and its entrypoint |
| 452 | * is set by load_image. This is a placeholder for the platform to change |
| 453 | * the entrypoint of BL31 and set SPSR and security state. |
| 454 | * On FVP we are only setting the security state, entrypoint |
| 455 | */ |
| 456 | extern void bl2_plat_set_bl31_ep_info(struct image_info *image, |
| 457 | struct entry_point_info *ep); |
| 458 | |
| 459 | /* |
| 460 | * Before calling this function BL32 is loaded in memory and its entrypoint |
| 461 | * is set by load_image. This is a placeholder for the platform to change |
| 462 | * the entrypoint of BL32 and set SPSR and security state. |
| 463 | * On FVP we are only setting the security state, entrypoint |
| 464 | */ |
| 465 | extern void bl2_plat_set_bl32_ep_info(struct image_info *image, |
| 466 | struct entry_point_info *ep); |
| 467 | |
| 468 | /* |
| 469 | * Before calling this function BL33 is loaded in memory and its entrypoint |
| 470 | * is set by load_image. This is a placeholder for the platform to change |
| 471 | * the entrypoint of BL33 and set SPSR and security state. |
| 472 | * On FVP we are only setting the security state, entrypoint |
| 473 | */ |
| 474 | extern void bl2_plat_set_bl33_ep_info(struct image_info *image, |
| 475 | struct entry_point_info *ep); |
| 476 | |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame^] | 477 | /* Gets the memory layout for BL32 */ |
| 478 | extern void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); |
| 479 | |
| 480 | /* Gets the memory layout for BL33 */ |
| 481 | extern void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); |
| 482 | |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 483 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 484 | #endif /*__ASSEMBLY__*/ |
| 485 | |
| 486 | #endif /* __PLATFORM_H__ */ |