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developer1033ea12019-04-10 21:09:26 +08001/*
developera21d47e2019-05-02 19:29:25 +08002 * Copyright (c) 2019, MediaTek Inc. All rights reserved.
developer1033ea12019-04-10 21:09:26 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <arch_helpers.h>
9#include <common/bl_common.h>
Julius Werner1f363212019-05-30 17:34:08 -070010#include <common/desc_image_load.h>
developer0d2cfca2019-08-23 10:23:34 +080011#include <devapc.h>
developer644ec1c2019-08-23 15:50:58 +080012#include <emi_mpu.h>
developer1033ea12019-04-10 21:09:26 +080013#include <plat/common/common_def.h>
14#include <drivers/console.h>
15#include <common/debug.h>
16#include <drivers/generic_delay_timer.h>
17#include <mcucfg.h>
developer3f3f1ab2019-05-02 22:26:22 +080018#include <mt_gic_v3.h>
Hung-Te Linc05a0b52019-05-02 21:42:41 +080019#include <lib/coreboot.h>
developer1033ea12019-04-10 21:09:26 +080020#include <lib/mmio.h>
developer555ed552019-08-21 22:49:49 +080021#include <mtk_mcdi.h>
developer1033ea12019-04-10 21:09:26 +080022#include <mtk_plat_common.h>
developera21d47e2019-05-02 19:29:25 +080023#include <mtspmc.h>
developer1033ea12019-04-10 21:09:26 +080024#include <plat_debug.h>
developer092c53a2019-05-03 16:59:07 +080025#include <plat_params.h>
developer1033ea12019-04-10 21:09:26 +080026#include <plat_private.h>
27#include <platform_def.h>
28#include <scu.h>
developer083fa242019-08-21 20:50:20 +080029#include <spm.h>
developer1033ea12019-04-10 21:09:26 +080030#include <drivers/ti/uart/uart_16550.h>
31
32static entry_point_info_t bl32_ep_info;
33static entry_point_info_t bl33_ep_info;
34
35static void platform_setup_cpu(void)
36{
37 mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001);
38
developerc3af6462019-08-21 21:16:29 +080039 /* Mcusys dcm control */
40 /* Enable pll plldiv dcm */
41 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg,
42 BUS_PLLDIV_DCM);
43 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg,
44 MP0_PLLDIV_DCM);
45 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg,
46 MP2_PLLDIV_DCM);
47 /* Enable mscib dcm */
48 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en,
49 MCSIB_CACTIVE_SEL_MASK, MCSIB_CACTIVE_SEL);
50 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en,
51 MCSIB_DCM_MASK, MCSIB_DCM);
52 /* Enable adb400 dcm */
53 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config,
54 CCI_ADB400_DCM_MASK, CCI_ADB400_DCM);
55 /* Enable bus clock dcm */
56 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl,
57 MCU_BUS_DCM);
58 /* Enable bus fabric dcm */
59 mmio_clrsetbits_32(
60 (uintptr_t)&mt8183_mcucfg->mcusys_bus_fabric_dcm_ctrl,
61 MCUSYS_BUS_FABRIC_DCM_MASK,
62 MCUSYS_BUS_FABRIC_DCM);
63 /* Enable l2c sram dcm */
64 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl,
65 L2C_SRAM_DCM);
66 /* Enable busmp0 sync dcm */
67 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config,
68 SYNC_DCM_MASK, SYNC_DCM);
69 /* Enable cntvalue dcm */
70 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl,
71 CNTVALUEB_DCM);
72 /* Enable dcm cluster stall */
73 mmio_clrsetbits_32(
74 (uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config,
75 MCUSYS_MAX_ACCESS_LATENCY_MASK,
76 MCUSYS_MAX_ACCESS_LATENCY);
77 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config,
78 MCU0_SYNC_DCM_STALL_WR_EN);
79 /* Enable rgu dcm */
80 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config,
81 CPUSYS_RGU_DCM_CINFIG);
developer1033ea12019-04-10 21:09:26 +080082}
83
84/*******************************************************************************
85 * Return a pointer to the 'entry_point_info' structure of the next image for
86 * the security state specified. BL33 corresponds to the non-secure image type
87 * while BL32 corresponds to the secure image type. A NULL pointer is returned
88 * if the image does not exist.
89 ******************************************************************************/
90entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
91{
92 entry_point_info_t *next_image_info;
93
94 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
Julius Werner1f363212019-05-30 17:34:08 -070095 assert(next_image_info->h.type == PARAM_EP);
developer1033ea12019-04-10 21:09:26 +080096
97 /* None of the images on this platform can have 0x0 as the entrypoint */
98 if (next_image_info->pc)
99 return next_image_info;
100 else
101 return NULL;
102}
103
104/*******************************************************************************
105 * Perform any BL31 early platform setup. Here is an opportunity to copy
106 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
107 * are lost (potentially). This needs to be done before the MMU is initialized
108 * so that the memory layout can be used while creating page tables.
109 * BL2 has flushed this information to memory, so we are guaranteed to pick up
110 * good data.
111 ******************************************************************************/
112void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
113 u_register_t arg2, u_register_t arg3)
114{
developer1033ea12019-04-10 21:09:26 +0800115 static console_16550_t console;
developer3f3f1ab2019-05-02 22:26:22 +0800116
developer092c53a2019-05-03 16:59:07 +0800117 params_early_setup(arg1);
118
Hung-Te Linc05a0b52019-05-02 21:42:41 +0800119#if COREBOOT
120 if (coreboot_serial.type)
121 console_16550_register(coreboot_serial.baseaddr,
122 coreboot_serial.input_hertz,
123 coreboot_serial.baud,
124 &console);
125#else
developer1033ea12019-04-10 21:09:26 +0800126 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
Hung-Te Linc05a0b52019-05-02 21:42:41 +0800127#endif
developer1033ea12019-04-10 21:09:26 +0800128
129 NOTICE("MT8183 bl31_setup\n");
130
Julius Werner1f363212019-05-30 17:34:08 -0700131 bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
developer1033ea12019-04-10 21:09:26 +0800132}
133
134
135/*******************************************************************************
136 * Perform any BL31 platform setup code
137 ******************************************************************************/
138void bl31_platform_setup(void)
139{
developer0d2cfca2019-08-23 10:23:34 +0800140 devapc_init();
141
developer644ec1c2019-08-23 15:50:58 +0800142 emi_mpu_init();
143
developer1033ea12019-04-10 21:09:26 +0800144 platform_setup_cpu();
145 generic_delay_timer_init();
developer3f3f1ab2019-05-02 22:26:22 +0800146
147 /* Initialize the GIC driver, CPU and distributor interfaces */
148 mt_gic_driver_init();
149 mt_gic_init();
developer88837432019-05-02 22:01:39 +0800150
151 /* Init mcsi SF */
152 plat_mtk_cci_init_sf();
developera21d47e2019-05-02 19:29:25 +0800153
154#if SPMC_MODE == 1
155 spmc_init();
156#endif
developer083fa242019-08-21 20:50:20 +0800157 spm_boot_init();
developer555ed552019-08-21 22:49:49 +0800158 mcdi_init();
developer1033ea12019-04-10 21:09:26 +0800159}
160
161/*******************************************************************************
162 * Perform the very early platform specific architectural setup here. At the
163 * moment this is only intializes the mmu in a quick and dirty way.
164 ******************************************************************************/
165void bl31_plat_arch_setup(void)
166{
developer88837432019-05-02 22:01:39 +0800167 plat_mtk_cci_init();
168 plat_mtk_cci_enable();
169
developer1033ea12019-04-10 21:09:26 +0800170 enable_scu(read_mpidr());
171
172 plat_configure_mmu_el3(BL_CODE_BASE,
173 BL_COHERENT_RAM_END - BL_CODE_BASE,
174 BL_CODE_BASE,
175 BL_CODE_END,
176 BL_COHERENT_RAM_BASE,
177 BL_COHERENT_RAM_END);
178}