Konstantin Porotchkin | 646b5cc | 2018-06-07 18:48:49 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
Konstantin Porotchkin | 91db290 | 2018-07-29 13:30:51 +0300 | [diff] [blame] | 8 | #include <armada_common.h> |
Konstantin Porotchkin | 646b5cc | 2018-06-07 18:48:49 +0300 | [diff] [blame] | 9 | #include <delay_timer.h> |
| 10 | #include <mmio.h> |
Konstantin Porotchkin | 91db290 | 2018-07-29 13:30:51 +0300 | [diff] [blame] | 11 | |
Konstantin Porotchkin | 646b5cc | 2018-06-07 18:48:49 +0300 | [diff] [blame] | 12 | /* |
| 13 | * If bootrom is currently at BLE there's no need to include the memory |
| 14 | * maps structure at this point |
| 15 | */ |
| 16 | #include <mvebu_def.h> |
| 17 | #ifndef IMAGE_BLE |
| 18 | |
| 19 | /***************************************************************************** |
| 20 | * GPIO Configuration |
| 21 | ***************************************************************************** |
| 22 | */ |
| 23 | #define MPP_CONTROL_REGISTER 0xf2440018 |
| 24 | #define MPP_CONTROL_MPP_SEL_52_MASK 0xf0000 |
| 25 | #define GPIO_DATA_OUT1_REGISTER 0xf2440140 |
| 26 | #define GPIO_DATA_OUT_EN_CTRL1_REGISTER 0xf2440144 |
| 27 | #define GPIO52_MASK 0x100000 |
| 28 | |
| 29 | /* Reset PCIe via GPIO number 52 */ |
| 30 | int marvell_gpio_config(void) |
| 31 | { |
| 32 | uint32_t reg; |
| 33 | |
| 34 | reg = mmio_read_32(MPP_CONTROL_REGISTER); |
| 35 | reg |= MPP_CONTROL_MPP_SEL_52_MASK; |
| 36 | mmio_write_32(MPP_CONTROL_REGISTER, reg); |
| 37 | |
| 38 | reg = mmio_read_32(GPIO_DATA_OUT1_REGISTER); |
| 39 | reg |= GPIO52_MASK; |
| 40 | mmio_write_32(GPIO_DATA_OUT1_REGISTER, reg); |
| 41 | |
| 42 | reg = mmio_read_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER); |
| 43 | reg &= ~GPIO52_MASK; |
| 44 | mmio_write_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER, reg); |
| 45 | udelay(100); |
| 46 | |
| 47 | return 0; |
| 48 | } |
| 49 | |
| 50 | /***************************************************************************** |
| 51 | * AMB Configuration |
| 52 | ***************************************************************************** |
| 53 | */ |
| 54 | struct addr_map_win amb_memory_map[] = { |
| 55 | /* CP1 SPI1 CS0 Direct Mode access */ |
| 56 | {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, |
| 57 | }; |
| 58 | |
| 59 | int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, |
| 60 | uintptr_t base) |
| 61 | { |
| 62 | *win = amb_memory_map; |
| 63 | if (*win == NULL) |
| 64 | *size = 0; |
| 65 | else |
| 66 | *size = ARRAY_SIZE(amb_memory_map); |
| 67 | |
| 68 | return 0; |
| 69 | } |
| 70 | #endif |
| 71 | |
| 72 | /***************************************************************************** |
| 73 | * IO WIN Configuration |
| 74 | ***************************************************************************** |
| 75 | */ |
| 76 | struct addr_map_win io_win_memory_map[] = { |
| 77 | /* CP1 (MCI0) internal regs */ |
| 78 | {0x00000000f4000000, 0x2000000, MCI_0_TID}, |
| 79 | #ifndef IMAGE_BLE |
| 80 | /* PCIe0 and SPI1_CS0 (RUNIT) on CP1*/ |
| 81 | {0x00000000f9000000, 0x2000000, MCI_0_TID}, |
| 82 | /* PCIe1 on CP1*/ |
| 83 | {0x00000000fb000000, 0x1000000, MCI_0_TID}, |
| 84 | /* PCIe2 on CP1*/ |
| 85 | {0x00000000fc000000, 0x1000000, MCI_0_TID}, |
| 86 | /* MCI 0 indirect window */ |
| 87 | {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID}, |
| 88 | /* MCI 1 indirect window */ |
| 89 | {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID}, |
| 90 | #endif |
| 91 | }; |
| 92 | |
| 93 | uint32_t marvell_get_io_win_gcr_target(int ap_index) |
| 94 | { |
| 95 | return PIDI_TID; |
| 96 | } |
| 97 | |
| 98 | int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, |
| 99 | uint32_t *size) |
| 100 | { |
| 101 | *win = io_win_memory_map; |
| 102 | if (*win == NULL) |
| 103 | *size = 0; |
| 104 | else |
| 105 | *size = ARRAY_SIZE(io_win_memory_map); |
| 106 | |
| 107 | return 0; |
| 108 | } |
| 109 | |
| 110 | #ifndef IMAGE_BLE |
| 111 | /***************************************************************************** |
| 112 | * IOB Configuration |
| 113 | ***************************************************************************** |
| 114 | */ |
| 115 | struct addr_map_win iob_memory_map_cp0[] = { |
| 116 | /* CP0 */ |
| 117 | /* PEX1_X1 window */ |
| 118 | {0x00000000f7000000, 0x1000000, PEX1_TID}, |
| 119 | /* PEX2_X1 window */ |
| 120 | {0x00000000f8000000, 0x1000000, PEX2_TID}, |
| 121 | /* PEX0_X4 window */ |
| 122 | {0x00000000f6000000, 0x1000000, PEX0_TID}, |
| 123 | {0x00000000c0000000, 0x30000000, PEX0_TID}, |
| 124 | {0x0000000800000000, 0x100000000, PEX0_TID}, |
| 125 | }; |
| 126 | |
| 127 | struct addr_map_win iob_memory_map_cp1[] = { |
| 128 | /* CP1 */ |
| 129 | /* SPI1_CS0 (RUNIT) window */ |
| 130 | {0x00000000f9000000, 0x1000000, RUNIT_TID}, |
| 131 | /* PEX1_X1 window */ |
| 132 | {0x00000000fb000000, 0x1000000, PEX1_TID}, |
| 133 | /* PEX2_X1 window */ |
| 134 | {0x00000000fc000000, 0x1000000, PEX2_TID}, |
| 135 | /* PEX0_X4 window */ |
| 136 | {0x00000000fa000000, 0x1000000, PEX0_TID} |
| 137 | }; |
| 138 | |
| 139 | int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, |
| 140 | uintptr_t base) |
| 141 | { |
| 142 | switch (base) { |
| 143 | case MVEBU_CP_REGS_BASE(0): |
| 144 | *win = iob_memory_map_cp0; |
| 145 | *size = ARRAY_SIZE(iob_memory_map_cp0); |
| 146 | return 0; |
| 147 | case MVEBU_CP_REGS_BASE(1): |
| 148 | *win = iob_memory_map_cp1; |
| 149 | *size = ARRAY_SIZE(iob_memory_map_cp1); |
| 150 | return 0; |
| 151 | default: |
| 152 | *size = 0; |
| 153 | *win = 0; |
| 154 | return 1; |
| 155 | } |
| 156 | } |
| 157 | #endif |
| 158 | |
| 159 | /***************************************************************************** |
| 160 | * CCU Configuration |
| 161 | ***************************************************************************** |
| 162 | */ |
| 163 | struct addr_map_win ccu_memory_map[] = { |
| 164 | #ifdef IMAGE_BLE |
| 165 | {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */ |
| 166 | #else |
| 167 | {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */ |
| 168 | {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ |
| 169 | {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */ |
| 170 | #endif |
| 171 | }; |
| 172 | |
| 173 | uint32_t marvell_get_ccu_gcr_target(int ap) |
| 174 | { |
| 175 | return DRAM_0_TID; |
| 176 | } |
| 177 | |
| 178 | int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, |
| 179 | uint32_t *size) |
| 180 | { |
| 181 | *win = ccu_memory_map; |
| 182 | *size = ARRAY_SIZE(ccu_memory_map); |
| 183 | |
| 184 | return 0; |
| 185 | } |
| 186 | |
| 187 | /* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */ |
| 188 | |
| 189 | /***************************************************************************** |
| 190 | * SKIP IMAGE Configuration |
| 191 | ***************************************************************************** |
| 192 | */ |
| 193 | void *plat_marvell_get_skip_image_data(void) |
| 194 | { |
| 195 | /* No recovery button on A8k-MCBIN board */ |
| 196 | return NULL; |
| 197 | } |