| Hari Nagalla | 3c0ef77 | 2022-08-22 14:04:52 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef BOARD_DEF_H |
| 8 | #define BOARD_DEF_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | /* The ports must be in order and contiguous */ |
| 13 | #define K3_CLUSTER0_CORE_COUNT U(4) |
| 14 | #define K3_CLUSTER1_CORE_COUNT U(4) |
| 15 | #define K3_CLUSTER2_CORE_COUNT U(0) |
| 16 | #define K3_CLUSTER3_CORE_COUNT U(0) |
| 17 | /* |
| 18 | * This RAM will be used for the bootloader including code, bss, and stacks. |
| 19 | * It may need to be increased if BL31 grows in size. |
| 20 | * |
| 21 | * The link addresses are determined by SEC_SRAM_BASE + offset. |
| 22 | * When ENABLE_PIE is set, the TF images can be loaded anywhere, so |
| 23 | * SEC_SRAM_BASE is really arbitrary. |
| 24 | * |
| 25 | * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that |
| 26 | * it matches to the physical address where BL31 is loaded, that is, |
| 27 | * SEC_SRAM_BASE should be the base address of the RAM region. |
| 28 | * |
| 29 | * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is |
| 30 | * defined as default for our platform. |
| 31 | */ |
| 32 | #define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */ |
| 33 | #define SEC_SRAM_SIZE UL(0x00020000) /* 128k */ |
| 34 | |
| 35 | #define PLAT_MAX_OFF_STATE U(2) |
| 36 | #define PLAT_MAX_RET_STATE U(1) |
| 37 | |
| 38 | #define PLAT_PROC_START_ID U(32) |
| 39 | |
| 40 | #define PLAT_PROC_DEVICE_START_ID U(202) |
| 41 | #define PLAT_CLUSTER_DEVICE_START_ID U(198) |
| 42 | |
| 43 | #endif /* BOARD_DEF_H */ |