Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 1 | /* |
David Cunado | 2e36de8 | 2017-01-19 10:26:16 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __PLATFORM_DEF_H__ |
| 8 | #define __PLATFORM_DEF_H__ |
| 9 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 10 | #include <arm_def.h> |
| 11 | #include <board_arm_def.h> |
| 12 | #include <common_def.h> |
| 13 | #include <tzc400.h> |
Douglas Raillard | 30a2694 | 2017-03-08 16:49:31 +0000 | [diff] [blame] | 14 | #include <utils.h> |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 15 | #include <v2m_def.h> |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 16 | #include "../fvp_def.h" |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 17 | |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 18 | /* Required platform porting definitions */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 19 | #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 20 | PLATFORM_CORE_COUNT) |
| 21 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 22 | #define PLATFORM_CORE_COUNT (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 23 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 24 | /* |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 25 | * Other platform porting definitions are provided by included headers |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 26 | */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 27 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 28 | /* |
| 29 | * Required ARM standard platform porting definitions |
| 30 | */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 31 | #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 32 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 33 | #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 |
| 34 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 35 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 36 | #define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000 |
| 37 | #define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 38 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 39 | /* No SCP in FVP */ |
David Cunado | 2e36de8 | 2017-01-19 10:26:16 +0000 | [diff] [blame] | 40 | #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0) |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 41 | |
David Cunado | 2e36de8 | 2017-01-19 10:26:16 +0000 | [diff] [blame] | 42 | #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) |
Juan Castillo | d227d8b | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 43 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 44 | /* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 45 | * Load address of BL33 for this platform port |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 46 | */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 47 | #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 48 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 49 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 50 | /* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 51 | * PL011 related constants |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 52 | */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 53 | #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE |
| 54 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 55 | |
Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 56 | #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE |
| 57 | #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ |
| 58 | |
| 59 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE |
| 60 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 61 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 62 | #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE |
| 63 | #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 64 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 65 | /* CCI related constants */ |
| 66 | #define PLAT_ARM_CCI_BASE 0x2c090000 |
| 67 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 |
| 68 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 |
Juan Castillo | e33ee5f | 2014-12-19 09:51:00 +0000 | [diff] [blame] | 69 | |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 70 | /* CCN related constants. Only CCN 502 is currently supported */ |
| 71 | #define PLAT_ARM_CCN_BASE 0x2e000000 |
| 72 | #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 |
| 73 | |
Vikram Kanigiri | a2cee03 | 2015-07-31 16:35:05 +0100 | [diff] [blame] | 74 | /* System timer related constants */ |
| 75 | #define PLAT_ARM_NSTIMER_FRAME_ID 1 |
| 76 | |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 77 | /* Mailbox base address */ |
| 78 | #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE |
| 79 | |
| 80 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 81 | /* TrustZone controller related constants |
| 82 | * |
| 83 | * Currently only filters 0 and 2 are connected on Base FVP. |
| 84 | * Filter 0 : CPU clusters (no access to DRAM by default) |
| 85 | * Filter 1 : not connected |
| 86 | * Filter 2 : LCDs (access to VRAM allowed by default) |
| 87 | * Filter 3 : not connected |
| 88 | * Programming unconnected filters will have no effect at the |
| 89 | * moment. These filter could, however, be connected in future. |
| 90 | * So care should be taken not to configure the unused filters. |
| 91 | * |
| 92 | * Allow only non-secure access to all DRAM to supported devices. |
| 93 | * Give access to the CPUs and Virtio. Some devices |
| 94 | * would normally use the default ID so allow that too. |
| 95 | */ |
Vikram Kanigiri | cab2f5e | 2015-07-31 14:50:36 +0100 | [diff] [blame] | 96 | #define PLAT_ARM_TZC_BASE 0x2a4a0000 |
Soby Mathew | 9c708b5 | 2016-02-26 14:23:19 +0000 | [diff] [blame] | 97 | #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 98 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 99 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 100 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ |
| 101 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ |
| 102 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ |
| 103 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ |
| 104 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 105 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 106 | /* |
| 107 | * GIC related constants to cater for both GICv2 and GICv3 instances of an |
| 108 | * FVP. They could be overriden at runtime in case the FVP implements the legacy |
| 109 | * VE memory map. |
| 110 | */ |
| 111 | #define PLAT_ARM_GICD_BASE BASE_GICD_BASE |
| 112 | #define PLAT_ARM_GICR_BASE BASE_GICR_BASE |
| 113 | #define PLAT_ARM_GICC_BASE BASE_GICC_BASE |
| 114 | |
| 115 | /* |
| 116 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 117 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 118 | * as Group 0 interrupts. |
| 119 | */ |
| 120 | #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ |
| 121 | FVP_IRQ_TZ_WDOG, \ |
| 122 | FVP_IRQ_SEC_SYS_TIMER |
| 123 | |
| 124 | #define PLAT_ARM_G0_IRQS ARM_G0_IRQS |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 125 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 126 | #endif /* __PLATFORM_DEF_H__ */ |