| Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2020, Broadcom |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CRMU_DEF_H |
| 8 | #define CRMU_DEF_H |
| 9 | |
| 10 | #define CRMU_REGS_BASE 0x66410000 |
| 11 | /* 32 kB IDRAM */ |
| 12 | #define CRMU_IDRAM_BASE_ADDR CRMU_REGS_BASE |
| 13 | #define CRMU_IDRAM_SIZE 0x8000 |
| 14 | /* 4 kB Scratch RAM */ |
| 15 | #define CRMU_SRAM_BASE (CRMU_IDRAM_BASE_ADDR + CRMU_IDRAM_SIZE) |
| 16 | #define CRMU_SRAM_SIZE 0x1000 |
| 17 | |
| 18 | #define CRMU_RESERVED_SPACE 0x3000 |
| 19 | #define CRMU_CORE_BASE (CRMU_SRAM_BASE + CRMU_SRAM_SIZE + \ |
| 20 | CRMU_RESERVED_SPACE) |
| 21 | |
| 22 | #define CRMU_SHARED_SRAM_BASE CRMU_SRAM_BASE |
| 23 | #define CRMU_SHARED_SRAM_SIZE 0x200 |
| 24 | #define CRMU_CFG_BASE (CRMU_SHARED_SRAM_BASE + \ |
| 25 | CRMU_SHARED_SRAM_SIZE) |
| 26 | |
| 27 | #define CRMU_PWR_GOOD_STATUS CRMU_CORE_BASE |
| 28 | #define CRMU_PWR_GOOD_STATUS__BBL_POWER_GOOD 0 |
| 29 | #define CRMU_ISO_CELL_CONTROL (CRMU_CORE_BASE + 0x4) |
| 30 | #define CRMU_ISO_CELL_CONTROL__CRMU_ISO_PDBBL 16 |
| 31 | #define CRMU_ISO_CELL_CONTROL__CRMU_ISO_PDBBL_TAMPER 24 |
| 32 | #define CRMU_SPRU_SOURCE_SEL_STAT (CRMU_CORE_BASE + 0xc) |
| 33 | #define CRMU_SPRU_SOURCE_SEL_STAT__SPRU_SOURCE_SELECT 0 |
| 34 | #define BSTI_BASE (CRMU_CORE_BASE + 0x28) |
| 35 | #define BSTI_CONTROL_OFFSET BSTI_BASE |
| 36 | #define BSTI_COMMAND_OFFSET (BSTI_BASE + 0x4) |
| 37 | |
| 38 | #define OCOTP_REGS_BASE (CRMU_CORE_BASE + 0x400) |
| 39 | |
| 40 | #define CRMU_TCI_BASE (CRMU_CORE_BASE + 0x800) |
| 41 | #define CRMU_SWREG_STATUS_ADDR (CRMU_TCI_BASE + 0x0c) |
| 42 | #define CRMU_CHIP_OTPC_STATUS (CRMU_TCI_BASE + 0x10) |
| 43 | #define CRMU_CHIP_OTPC_STATUS__OTP_BISR_LOAD_DONE 19 |
| 44 | #define CRMU_BISR_PDG_MASK (CRMU_TCI_BASE + 0x4c) |
| 45 | #define CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST0 2 |
| 46 | #define CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST1 3 |
| 47 | #define CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST2 4 |
| 48 | #define CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST3 0 |
| 49 | #define CRMU_POWER_POLL (CRMU_TCI_BASE + 0x60) |
| 50 | #define CRMU_OTP_STATUS CRMU_POWER_POLL |
| 51 | #define CRMU_OTP_STATUS_BIT 1 |
| 52 | #define CRMU_DDR_PHY_AON_CTRL (CRMU_TCI_BASE + 0x64) |
| 53 | #define CRMU_DDRPHY2_HW_RESETN_R BIT(21) |
| 54 | #define CRMU_DDRPHY2_PWROKIN_PHY_R BIT(20) |
| 55 | #define CRMU_DDRPHY2_PWRONIN_PHY_R BIT(19) |
| 56 | #define CRMU_DDRPHY2_ISO_PHY_DFI_R BIT(18) |
| 57 | #define CRMU_DDRPHY2_ISO_PHY_REGS_R BIT(17) |
| 58 | #define CRMU_DDRPHY2_ISO_PHY_PLL_R BIT(16) |
| 59 | #define CRMU_DDRPHY1_HW_RESETN_R BIT(13) |
| 60 | #define CRMU_DDRPHY1_PWROKIN_PHY_R BIT(12) |
| 61 | #define CRMU_DDRPHY1_PWRONIN_PHY_R BIT(11) |
| 62 | #define CRMU_DDRPHY1_ISO_PHY_DFI_R BIT(10) |
| 63 | #define CRMU_DDRPHY1_ISO_PHY_REGS_R BIT(9) |
| 64 | #define CRMU_DDRPHY1_ISO_PHY_PLL_R BIT(8) |
| 65 | #define CRMU_DDRPHY0_HW_RESETN_R BIT(5) |
| 66 | #define CRMU_DDRPHY0_PWROKIN_PHY_R BIT(4) |
| 67 | #define CRMU_DDRPHY0_PWRONIN_PHY_R BIT(3) |
| 68 | #define CRMU_DDRPHY0_ISO_PHY_DFI_R BIT(2) |
| 69 | #define CRMU_DDRPHY0_ISO_PHY_REGS_R BIT(1) |
| 70 | #define CRMU_DDRPHY0_ISO_PHY_PLL_R BIT(0) |
| 71 | #define CRMU_EMEM_RESET_N_R BIT(16) |
| 72 | #define CRMU_EMEM_PRESET_N_R BIT(0) |
| 73 | #define CRMU_SWREG_CTRL_ADDR (CRMU_TCI_BASE + 0x6c) |
| 74 | #define CRMU_AON_CTRL1 (CRMU_TCI_BASE + 0x70) |
| 75 | #define CRMU_AON_CTRL1__LCPLL1_ISO_IN 18 |
| 76 | #define CRMU_AON_CTRL1__LCPLL1_PWRON_LDO 19 |
| 77 | #define CRMU_AON_CTRL1__LCPLL1_PWR_ON 20 |
| 78 | #define CRMU_AON_CTRL1__LCPLL0_ISO_IN 21 |
| 79 | #define CRMU_AON_CTRL1__LCPLL0_PWRON_LDO 22 |
| 80 | #define CRMU_AON_CTRL1__LCPLL0_PWR_ON 23 |
| 81 | #define CRMU_PCIE_LCPLL_PWR_ON_SHIFT 29 |
| 82 | #define CRMU_PCIE_LCPLL_PWR_ON_MASK BIT(CRMU_PCIE_LCPLL_PWR_ON_SHIFT) |
| 83 | #define CRMU_PCIE_LCPLL_PWRON_LDO_SHIFT 28 |
| 84 | #define CRMU_PCIE_LCPLL_PWRON_LDO_MASK BIT(CRMU_PCIE_LCPLL_PWRON_LDO_SHIFT) |
| 85 | #define CRMU_PCIE_LCPLL_ISO_IN_SHIFT 27 |
| 86 | #define CRMU_PCIE_LCPLL_ISO_IN_MASK BIT(CRMU_PCIE_LCPLL_ISO_IN_SHIFT) |
| 87 | #define CRMU_MASTER_AXI_ARUSER_CONFIG (CRMU_TCI_BASE + 0x74) |
| 88 | #define CRMU_MASTER_AXI_AWUSER_CONFIG (CRMU_TCI_BASE + 0x78) |
| 89 | #define CRMU_DDR_PHY_AON_CTRL_1 (CRMU_TCI_BASE + 0x8c) |
| 90 | |
| 91 | #define CDRU_BASE_ADDR (CRMU_CORE_BASE + 0x1000) |
| 92 | #define CDRU_MISC_RESET_CONTROL CDRU_BASE_ADDR |
| 93 | #define CDRU_MISC_RESET_CONTROL_TS_RESET_N 16 |
| 94 | #define CDRU_MISC_RESET_CONTROL__CDRU_USBSS_RESET_N 14 |
| 95 | #define CDRU_MISC_RESET_CONTROL__CDRU_SATA_RESET_N_R 15 |
| 96 | #define CDRU_MISC_RESET_CONTROL__CDRU_MHB_RESET_N_R 13 |
| 97 | #define CDRU_MISC_RESET_CONTROL__CDRU_PCIE_RESET_N_R 3 |
| 98 | #define CDRU_MISC_RESET_CONTROL__CDRU_PM_RESET_N_R 2 |
| 99 | #define CDRU_MISC_RESET_CONTROL__CDRU_NITRO_RESET_N_R 1 |
| 100 | |
| 101 | #define CDRU_PROC_EVENT_CLEAR (CDRU_BASE_ADDR + 0x48) |
| 102 | #define CDRU_PROC_EVENT_CLEAR__IH0_CDRU_STANDBYWFIL2 0 |
| 103 | #define CDRU_PROC_EVENT_CLEAR__IH0_CDRU_STANDBYWFI 3 |
| 104 | #define CDRU_PROC_EVENT_CLEAR__IH1_CDRU_STANDBYWFIL2 5 |
| 105 | #define CDRU_PROC_EVENT_CLEAR__IH1_CDRU_STANDBYWFI 8 |
| 106 | #define CDRU_PROC_EVENT_CLEAR__IH2_CDRU_STANDBYWFIL2 10 |
| 107 | #define CDRU_PROC_EVENT_CLEAR__IH2_CDRU_STANDBYWFI 13 |
| 108 | #define CDRU_PROC_EVENT_CLEAR__IH3_CDRU_STANDBYWFIL2 15 |
| 109 | #define CDRU_PROC_EVENT_CLEAR__IH3_CDRU_STANDBYWFI 18 |
| 110 | |
| 111 | #define CDRU_CHIP_STRAP_CTRL (CDRU_BASE_ADDR + 0x50) |
| 112 | #define CDRU_CHIP_STRAP_CTRL__SOFTWARE_OVERRIDE 31 |
| 113 | |
| 114 | #define CDRU_CHIP_IO_PAD_CONTROL (CDRU_BASE_ADDR + 0x58) |
| 115 | #define CDRU_CHIP_IO_PAD_CONTROL__CDRU_IOMUX_FORCE_PDN_R 8 |
| 116 | #define CDRU_CHIP_IO_PAD_CONTROL__CDRU_IOMUX_FORCE_PAD_IN_R 0 |
| 117 | |
| 118 | #define CDRU_CHIP_STRAP_DATA_LSW (CDRU_BASE_ADDR + 0x5c) |
| 119 | #define CDRU_CHIP_STRAP_DATA_LSW__BISR_BYPASS_MODE 18 |
| 120 | #define CDRU_CHIP_STRAP_DATA_LSW__NIC_MODE_MASK BIT(8) |
| 121 | #define CDRU_CHIP_STRAP_DATA_LSW_PAD_USB_MODE BIT(26) |
| 122 | |
| 123 | #define CDRU_CHIP_STRAP_DATA (CDRU_BASE_ADDR + 0x5c) |
| 124 | #define CDRU_DDR0_CONTROL_OFFSET (CDRU_BASE_ADDR + 0xb8) |
| 125 | #define CDRU_DDR1_CONTROL_OFFSET (CDRU_BASE_ADDR + 0xbc) |
| 126 | #define CDRU_DDR2_CONTROL_OFFSET (CDRU_BASE_ADDR + 0xc0) |
| 127 | #define CRMU_SW_POR_RESET_CTRL (CDRU_BASE_ADDR + 0x100) |
| 128 | |
| 129 | #define CDRU_GENPLL2_CONTROL1 (CDRU_BASE_ADDR + 0x1b0) |
| 130 | #define CDRU_GENPLL2_CONTROL1__CHNL6_FS4_CLK BIT(11) |
| 131 | #define CDRU_GENPLL5_CONTROL1 (CDRU_BASE_ADDR + 0x24c) |
| 132 | #define CDRU_GENPLL5_CONTROL1__CHNL0_DME_CLK BIT(6) |
| 133 | #define CDRU_GENPLL5_CONTROL1__CHNL1_CRYPTO_AE_CLK BIT(7) |
| 134 | #define CDRU_GENPLL5_CONTROL1__CHNL2_RAID_AE_CLK BIT(8) |
| 135 | |
| 136 | #define CDRU_NITRO_CONTROL (CDRU_BASE_ADDR + 0x2c4) |
| 137 | #define CDRU_NITRO_CONTROL__CDRU_NITRO_SEC_MODE_R 20 |
| 138 | #define CDRU_NITRO_CONTROL__CDRU_NITRO_SEC_OVERRIDE_R 16 |
| 139 | |
| 140 | #define CDRU_MISC_CLK_ENABLE_CONTROL (CDRU_BASE_ADDR + 0x2c8) |
| 141 | #define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_EMEM2_CLK_EN_R 11 |
| 142 | #define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_EMEM1_CLK_EN_R 10 |
| 143 | #define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_EMEM0_CLK_EN_R 9 |
| 144 | #define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_SATA_CLK_EN_R 8 |
| 145 | #define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_USBSS_CLK_EN_R 7 |
| 146 | #define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_MHB_CLK_EN_R 6 |
| 147 | #define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_HSLS_CLK_EN_R 5 |
| 148 | #define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_SCR_CLK_EN_R 4 |
| 149 | #define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_FS4_CLK_EN_R 3 |
| 150 | #define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_PCIE_CLK_EN_R 2 |
| 151 | #define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_PM_CLK_EN_R 1 |
| 152 | #define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_NITRO_CLK_EN_R 0 |
| 153 | |
| 154 | #define CDRU_CCN_REGISTER_CONTROL_1 (CDRU_BASE_ADDR + 0x324) |
| 155 | #define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_EMEM0_BIT 6 |
| 156 | #define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_EMEM1_BIT 5 |
| 157 | #define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_EMEM2_BIT 4 |
| 158 | |
| 159 | #define CDRU_CHIP_TOP_SPARE_REG0 (CDRU_BASE_ADDR + 0x378) |
| 160 | #define CDRU_CHIP_TOP_SPARE_REG1 (CDRU_BASE_ADDR + 0x37c) |
| 161 | |
| 162 | #define CENTRAL_TIMER_BASE (CRMU_CORE_BASE + 0x5000) |
| 163 | #define CENTRAL_TIMER_CTRL (CENTRAL_TIMER_BASE + 0x0) |
| 164 | #define CENTRAL_TIMER_GET_L (CENTRAL_TIMER_BASE + 0x4) |
| 165 | #define CENTRAL_TIMER_GET_L0 (CENTRAL_TIMER_BASE + 0x8) /* SCR STM */ |
| 166 | #define CENTRAL_TIMER_GET_L1 (CENTRAL_TIMER_BASE + 0xC) /* FS STM */ |
| 167 | #define CENTRAL_TIMER_GET_L2 (CENTRAL_TIMER_BASE + 0x10) /* iHost0 */ |
| 168 | #define CENTRAL_TIMER_GET_L3 (CENTRAL_TIMER_BASE + 0x14) /* iHost1 */ |
| 169 | #define CENTRAL_TIMER_GET_L4 (CENTRAL_TIMER_BASE + 0x18) /* iHost2 */ |
| 170 | #define CENTRAL_TIMER_GET_L5 (CENTRAL_TIMER_BASE + 0x1C) /* iHost3 */ |
| 171 | #define CENTRAL_TIMER_GET_H (CENTRAL_TIMER_BASE + 0x28) |
| 172 | #define CENTRAL_TIMER_SAT_TMR_ENA (CENTRAL_TIMER_BASE + 0x34) |
| 173 | #define CENTRAL_TIMER_GET_IHOST_ENA_BASE (CENTRAL_TIMER_GET_L2) |
| 174 | |
| 175 | #define CRMU_WDT_REGS_BASE (CRMU_CORE_BASE + 0x6000) |
| 176 | |
| 177 | #define CRMU_MAIL_BOX0 (CRMU_CORE_BASE + 0x8024) |
| 178 | #define CRMU_MAIL_BOX1 (CRMU_CORE_BASE + 0x8028) |
| 179 | #define CRMU_READ_MAIL_BOX0 (CRMU_CORE_BASE + 0x802c) |
| 180 | #define CRMU_READ_MAIL_BOX1 (CRMU_CORE_BASE + 0x8030) |
| 181 | #define AP_TO_SCP_MAILBOX1 CRMU_MAIL_BOX1 |
| 182 | #define SCP_TO_AP_MAILBOX1 CRMU_READ_MAIL_BOX1 |
| 183 | #define CRMU_IHOST_POWER_CONFIG (CRMU_CORE_BASE + 0x8038) |
| 184 | #define CRMU_RESET_EVENT_LOG (CRMU_CORE_BASE + 0x8064) |
| 185 | #define CRMU_SOFT_RESET_CTRL (CRMU_CORE_BASE + 0x8090) |
| 186 | #define CRMU_SOFT_RESET_CTRL__SOFT_PWR_UP_RST 0 |
| 187 | #define CRMU_SOFT_RESET_CTRL__SOFT_SYS_RST 1 |
| 188 | #define CRMU_SPARE_REG_0 (CRMU_CORE_BASE + 0x80b8) |
| 189 | #define CRMU_SPARE_REG_1 (CRMU_CORE_BASE + 0x80bc) |
| 190 | #define CRMU_SPARE_REG_2 (CRMU_CORE_BASE + 0x80c0) |
| 191 | #define CRMU_SPARE_REG_3 (CRMU_CORE_BASE + 0x80c4) |
| 192 | #define CRMU_SPARE_REG_4 (CRMU_CORE_BASE + 0x80c8) |
| 193 | #define CRMU_SPARE_REG_5 (CRMU_CORE_BASE + 0x80cc) |
| 194 | #define CRMU_CORE_ADDR_RANGE0_LOW (CRMU_CORE_BASE + 0x8c30) |
| 195 | #define CRMU_CORE_ADDR_RANGE1_LOW (CRMU_CORE_BASE + 0x8c38) |
| 196 | #define CRMU_CORE_ADDR_RANGE2_LOW (CRMU_CORE_BASE + 0x8c40) |
| 197 | #define CRMU_IHOST_SW_PERSISTENT_REG0 (CRMU_CORE_BASE + 0x8c54) |
| 198 | #define CRMU_IHOST_SW_PERSISTENT_REG1 (CRMU_CORE_BASE + 0x8c58) |
| 199 | #define CRMU_IHOST_SW_PERSISTENT_REG2 (CRMU_CORE_BASE + 0x8c5c) |
| 200 | #define CRMU_IHOST_SW_PERSISTENT_REG3 (CRMU_CORE_BASE + 0x8c60) |
| 201 | #define CRMU_IHOST_SW_PERSISTENT_REG4 (CRMU_CORE_BASE + 0x8c64) |
| 202 | #define CRMU_IHOST_SW_PERSISTENT_REG5 (CRMU_CORE_BASE + 0x8c68) |
| 203 | #define CRMU_IHOST_SW_PERSISTENT_REG6 (CRMU_CORE_BASE + 0x8c6c) |
| 204 | #define CRMU_IHOST_SW_PERSISTENT_REG7 (CRMU_CORE_BASE + 0x8c70) |
| 205 | #define CRMU_BBL_AUTH_CHECK (CRMU_CORE_BASE + 0x8c78) |
| 206 | #define CRMU_SOTP_NEUTRALIZE_ENABLE (CRMU_CORE_BASE + 0x8c84) |
| 207 | #define CRMU_IHOST_SW_PERSISTENT_REG8 (CRMU_CORE_BASE + 0x8c88) |
| 208 | #define CRMU_IHOST_SW_PERSISTENT_REG9 (CRMU_CORE_BASE + 0x8c8c) |
| 209 | #define CRMU_IHOST_SW_PERSISTENT_REG10 (CRMU_CORE_BASE + 0x8c90) |
| 210 | #define CRMU_IHOST_SW_PERSISTENT_REG11 (CRMU_CORE_BASE + 0x8c94) |
| 211 | |
| 212 | #define CNT_CONTROL_BASE (CRMU_CORE_BASE + 0x9000) |
| 213 | #define CNTCR (CNT_CONTROL_BASE) |
| 214 | #define CNTCR__EN BIT(0) |
| 215 | |
| 216 | #define SPRU_BBL_WDATA (CRMU_CORE_BASE + 0xa000) |
| 217 | #define SPRU_BBL_CMD (CRMU_CORE_BASE + 0xa004) |
| 218 | #define SPRU_BBL_CMD__IND_SOFT_RST_N 10 |
| 219 | #define SPRU_BBL_CMD__IND_WR 11 |
| 220 | #define SPRU_BBL_CMD__BBL_ADDR_R 0 |
| 221 | #define SPRU_BBL_CMD__IND_RD 12 |
| 222 | #define SPRU_BBL_CMD__BBL_ADDR_R 0 |
| 223 | #define SPRU_BBL_STATUS (CRMU_CORE_BASE + 0xa008) |
| 224 | #define SPRU_BBL_STATUS__ACC_DONE 0 |
| 225 | #define SPRU_BBL_RDATA (CRMU_CORE_BASE + 0xa00c) |
| 226 | |
| 227 | #endif /* CRMU_DEF_H */ |