| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CORTEX_A710_H |
| 8 | #define CORTEX_A710_H |
| 9 | |
| 10 | #define CORTEX_A710_MIDR U(0x410FD470) |
| 11 | |
| 12 | /******************************************************************************* |
| 13 | * CPU Extended Control register specific definitions |
| 14 | ******************************************************************************/ |
| 15 | #define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4 |
| nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 16 | #define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 17 | |
| 18 | /******************************************************************************* |
| 19 | * CPU Power Control register specific definitions |
| 20 | ******************************************************************************/ |
| 21 | #define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 22 | #define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| 23 | |
| Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 24 | /******************************************************************************* |
| 25 | * CPU Auxiliary Control register specific definitions. |
| 26 | ******************************************************************************/ |
| 27 | #define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0 |
| nayanpatel-arm | f2dce0e | 2021-09-22 12:35:03 -0700 | [diff] [blame] | 28 | #define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) |
| Bipin Ravi | 32705b1 | 2022-02-06 02:32:54 -0600 | [diff] [blame] | 29 | #define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) |
| nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 30 | |
| 31 | /******************************************************************************* |
| johpow01 | 7249fd0 | 2022-02-28 18:34:04 -0600 | [diff] [blame] | 32 | * CPU Auxiliary Control register 2 specific definitions. |
| 33 | ******************************************************************************/ |
| 34 | #define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1 |
| 35 | |
| 36 | /******************************************************************************* |
| 37 | * CPU Auxiliary Control register 5 specific definitions. |
| nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 38 | ******************************************************************************/ |
| 39 | #define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0 |
| 40 | #define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) |
| Bipin Ravi | d53069b | 2022-02-06 03:11:44 -0600 | [diff] [blame] | 41 | #define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) |
| Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 42 | |
| nayanpatel-arm | f2dce0e | 2021-09-22 12:35:03 -0700 | [diff] [blame] | 43 | /******************************************************************************* |
| 44 | * CPU Auxiliary Control register specific definitions. |
| 45 | ******************************************************************************/ |
| 46 | #define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5 |
| 47 | #define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) |
| 48 | #define CPUECTLR2_EL1_PF_MODE_LSB U(11) |
| 49 | #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) |
| 50 | |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 51 | #endif /* CORTEX_A710_H */ |