blob: b880e1bc73b858017876bd58e11b3a595a069403 [file] [log] [blame]
Anson Huang73b18532018-06-05 16:13:45 +08001/*
Deepika Bhavnani92efb232019-12-13 10:47:06 -06002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Anson Huang73b18532018-06-05 16:13:45 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Anson Huang73b18532018-06-05 16:13:45 +080011
12#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
13#define PLATFORM_LINKER_ARCH aarch64
14
15#define PLATFORM_STACK_SIZE 0x400
16#define CACHE_WRITEBACK_GRANULE 64
17
Deepika Bhavnani92efb232019-12-13 10:47:06 -060018#define PLAT_PRIMARY_CPU U(0x0)
19#define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
20#define PLATFORM_CLUSTER_COUNT U(1)
21#define PLATFORM_CORE_COUNT U(4)
22#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
23#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
Anson Huang73b18532018-06-05 16:13:45 +080024
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010025#define PWR_DOMAIN_AT_MAX_LVL U(1)
26#define PLAT_MAX_PWR_LVL U(2)
27#define PLAT_MAX_OFF_STATE U(2)
28#define PLAT_MAX_RET_STATE U(1)
Anson Huang73b18532018-06-05 16:13:45 +080029
30#define BL31_BASE 0x80000000
31#define BL31_LIMIT 0x80020000
32
33#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
34#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
35
36#define MAX_XLAT_TABLES 8
37#define MAX_MMAP_REGIONS 8
38
39#define PLAT_GICD_BASE 0x51a00000
Anson Huang73b18532018-06-05 16:13:45 +080040#define PLAT_GICR_BASE 0x51b00000
Igor Opaniuk72d86082020-03-23 17:21:05 +020041
42#if defined(IMX_USE_UART0)
Anson Huang73b18532018-06-05 16:13:45 +080043#define IMX_BOOT_UART_BASE 0x5a060000
Igor Opaniuk72d86082020-03-23 17:21:05 +020044#elif defined(IMX_USE_UART3)
45#define IMX_BOOT_UART_BASE 0x5a090000
46#else
47#error "Provide proper UART configuration in IMX_DEBUG_UART"
48#endif
49
Anson Huang73b18532018-06-05 16:13:45 +080050#define IMX_BOOT_UART_BAUDRATE 115200
51#define IMX_BOOT_UART_CLK_IN_HZ 24000000
52#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE
53#define PLAT__CRASH_UART_CLK_IN_HZ 24000000
54#define IMX_CONSOLE_BAUDRATE 115200
55#define SC_IPC_BASE 0x5d1b0000
Anson Huang3f2f3da2019-01-24 16:50:02 +080056#define IMX_GPT0_LPCG_BASE 0x5d540000
57#define IMX_GPT0_BASE 0x5d140000
58#define IMX_WUP_IRQSTR_BASE 0x51090000
59#define IMX_REG_BASE 0x50000000
60#define IMX_REG_SIZE 0x10000000
Anson Huang73b18532018-06-05 16:13:45 +080061
62#define COUNTER_FREQUENCY 8000000
63
64/* non-secure u-boot base */
65#define PLAT_NS_IMAGE_OFFSET 0x80020000
Igor Opaniuk72d86082020-03-23 17:21:05 +020066#define DEBUG_CONSOLE_A35 DEBUG_CONSOLE
Anson Huang73b18532018-06-05 16:13:45 +080067
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010068#endif /* PLATFORM_DEF_H */