Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 1 | /* |
Michal Simek | 2a47faa | 2023-04-14 08:43:51 +0200 | [diff] [blame] | 2 | * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 3 | * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. |
Jay Buddhabhatti | 6a44ad0 | 2023-02-28 01:23:04 -0800 | [diff] [blame] | 4 | * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 5 | * |
| 6 | * SPDX-License-Identifier: BSD-3-Clause |
| 7 | */ |
| 8 | |
| 9 | #ifndef PLATFORM_DEF_H |
| 10 | #define PLATFORM_DEF_H |
| 11 | |
| 12 | #include <arch.h> |
| 13 | #include "versal_net_def.h" |
| 14 | |
| 15 | /******************************************************************************* |
| 16 | * Generic platform constants |
| 17 | ******************************************************************************/ |
| 18 | |
| 19 | /* Size of cacheable stacks */ |
| 20 | #define PLATFORM_STACK_SIZE U(0x440) |
| 21 | |
| 22 | #define PLATFORM_CLUSTER_COUNT U(4) |
| 23 | #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) /* 4 CPUs per cluster */ |
| 24 | |
| 25 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER) |
| 26 | |
| 27 | #define PLAT_MAX_PWR_LVL U(2) |
| 28 | #define PLAT_MAX_RET_STATE U(1) |
| 29 | #define PLAT_MAX_OFF_STATE U(2) |
| 30 | |
| 31 | /******************************************************************************* |
| 32 | * BL31 specific defines. |
| 33 | ******************************************************************************/ |
| 34 | /* |
| 35 | * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if |
| 36 | * present). BL31_BASE is calculated using the current BL31 debug size plus a |
| 37 | * little space for growth. |
| 38 | */ |
| 39 | #ifndef VERSAL_NET_ATF_MEM_BASE |
| 40 | # define BL31_BASE U(0xBBF00000) |
| 41 | # define BL31_LIMIT U(0xBBFFFFFF) |
| 42 | #else |
| 43 | # define BL31_BASE U(VERSAL_NET_ATF_MEM_BASE) |
| 44 | # define BL31_LIMIT U(VERSAL_NET_ATF_MEM_BASE + VERSAL_NET_ATF_MEM_SIZE - 1) |
| 45 | # ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE |
| 46 | # define BL31_PROGBITS_LIMIT U(VERSAL_NET_ATF_MEM_BASE + \ |
| 47 | VERSAL_NET_ATF_MEM_PROGBITS_SIZE - 1) |
| 48 | # endif |
| 49 | #endif |
| 50 | |
| 51 | /******************************************************************************* |
| 52 | * BL32 specific defines. |
| 53 | ******************************************************************************/ |
| 54 | #ifndef VERSAL_NET_BL32_MEM_BASE |
| 55 | # define BL32_BASE U(0x60000000) |
| 56 | # define BL32_LIMIT U(0x7FFFFFFF) |
| 57 | #else |
| 58 | # define BL32_BASE U(VERSAL_NET_BL32_MEM_BASE) |
| 59 | # define BL32_LIMIT U(VERSAL_NET_BL32_MEM_BASE + VERSAL_NET_BL32_MEM_SIZE - 1) |
| 60 | #endif |
| 61 | |
| 62 | /******************************************************************************* |
| 63 | * BL33 specific defines. |
| 64 | ******************************************************************************/ |
| 65 | #ifndef PRELOADED_BL33_BASE |
| 66 | # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) |
| 67 | #else |
| 68 | # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) |
| 69 | #endif |
| 70 | |
| 71 | /******************************************************************************* |
| 72 | * TSP specific defines. |
| 73 | ******************************************************************************/ |
| 74 | #define TSP_SEC_MEM_BASE BL32_BASE |
| 75 | #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1U) |
| 76 | |
| 77 | /* ID of the secure physical generic timer interrupt used by the TSP */ |
| 78 | #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER |
| 79 | |
| 80 | /******************************************************************************* |
| 81 | * Platform specific page table and MMU setup constants |
| 82 | ******************************************************************************/ |
| 83 | #define PLAT_DDR_LOWMEM_MAX U(0x80000000) |
| 84 | |
| 85 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) |
| 86 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) |
| 87 | #if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) |
| 88 | #define MAX_MMAP_REGIONS U(10) |
| 89 | #else |
| 90 | #define MAX_MMAP_REGIONS U(9) |
| 91 | #endif |
| 92 | |
| 93 | #define MAX_XLAT_TABLES U(8) |
| 94 | |
| 95 | #define CACHE_WRITEBACK_SHIFT U(6) |
| 96 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 97 | |
Jay Buddhabhatti | 6a44ad0 | 2023-02-28 01:23:04 -0800 | [diff] [blame] | 98 | #define PLAT_GICD_BASE_VALUE U(0xE2000000) |
| 99 | #define PLAT_GICR_BASE_VALUE U(0xE2060000) |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 100 | |
| 101 | /* |
| 102 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 103 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 104 | * as Group 0 interrupts. |
| 105 | */ |
Trung Tran | 3980f19 | 2023-03-14 11:59:37 -0700 | [diff] [blame] | 106 | #define PLAT_VERSAL_NET_IPI_IRQ 89 |
| 107 | #define PLAT_VERSAL_IPI_IRQ PLAT_VERSAL_NET_IPI_IRQ |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 108 | |
| 109 | #define PLAT_VERSAL_NET_G1S_IRQ_PROPS(grp) \ |
| 110 | INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 111 | GIC_INTR_CFG_LEVEL) |
| 112 | |
Trung Tran | 3980f19 | 2023-03-14 11:59:37 -0700 | [diff] [blame] | 113 | #define PLAT_VERSAL_NET_G0_IRQ_PROPS(grp) \ |
| 114 | INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 115 | GIC_INTR_CFG_EDGE), \ |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 116 | |
Jay Buddhabhatti | a63b354 | 2023-02-28 02:22:02 -0800 | [diff] [blame] | 117 | #define IRQ_MAX 200U |
| 118 | |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 119 | #endif /* PLATFORM_DEF_H */ |