| developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <mcucfg.h> |
| 33 | #include <mmio.h> |
| 34 | |
| 35 | void disable_scu(unsigned long mpidr) |
| 36 | { |
| 37 | if (mpidr & MPIDR_CLUSTER_MASK) |
| 38 | mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, |
| 39 | MP1_ACINACTM); |
| 40 | else |
| 41 | mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, |
| 42 | MP0_ACINACTM); |
| 43 | } |
| 44 | |
| 45 | void enable_scu(unsigned long mpidr) |
| 46 | { |
| 47 | if (mpidr & MPIDR_CLUSTER_MASK) |
| 48 | mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, |
| 49 | MP1_ACINACTM); |
| 50 | else |
| 51 | mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, |
| 52 | MP0_ACINACTM); |
| 53 | } |