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Jiafei Pan46367ad2018-03-02 07:23:30 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +01008#include <bl_common.h>
Jiafei Pan46367ad2018-03-02 07:23:30 +00009#include <console.h>
Jiafei Pan46367ad2018-03-02 07:23:30 +000010#include <gicv2.h>
Antonio Nino Diaz53dec732018-09-25 14:54:23 +010011#include <interrupt_props.h>
12#include <mmio.h>
13
Jiafei Pan46367ad2018-03-02 07:23:30 +000014#include "ls_16550.h"
15#include "plat_ls.h"
16#include "soc.h"
17
Jiafei Pan46367ad2018-03-02 07:23:30 +000018/*
19 * Placeholder variables for copying the arguments that have been passed to
20 * BL31 from BL2.
21 */
22static entry_point_info_t bl32_image_ep_info;
23static entry_point_info_t bl33_image_ep_info;
24
Antonio Nino Diaz53dec732018-09-25 14:54:23 +010025static const interrupt_prop_t g0_interrupt_props[] = {
26 INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
27 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
Jiafei Pan46367ad2018-03-02 07:23:30 +000028};
29
30gicv2_driver_data_t ls_gic_data = {
31 .gicd_base = GICD_BASE,
32 .gicc_base = GICC_BASE,
Antonio Nino Diaz53dec732018-09-25 14:54:23 +010033 .interrupt_props = g0_interrupt_props,
34 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
Jiafei Pan46367ad2018-03-02 07:23:30 +000035};
36
37
38/*******************************************************************************
39 * Return a pointer to the 'entry_point_info' structure of the next image for the
40 * security state specified. BL33 corresponds to the non-secure image type
41 * while BL32 corresponds to the secure image type. A NULL pointer is returned
42 * if the image does not exist.
43 ******************************************************************************/
44entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
45{
46 entry_point_info_t *next_image_info;
47
48 assert(sec_state_is_valid(type));
49 next_image_info = (type == NON_SECURE)
50 ? &bl33_image_ep_info : &bl32_image_ep_info;
51
52 if (next_image_info->pc)
53 return next_image_info;
54 else
55 return NULL;
56}
57
58/*******************************************************************************
59 * Perform any BL31 early platform setup common to Layerscape platforms.
60 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
John Tsichritzisd653d332018-09-14 10:34:57 +010061 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be
Jiafei Pan46367ad2018-03-02 07:23:30 +000062 * done before the MMU is initialized so that the memory layout can be used
63 * while creating page tables. BL2 has flushed this information to memory, so
64 * we are guaranteed to pick up good data.
65 ******************************************************************************/
66void ls_bl31_early_platform_setup(void *from_bl2,
67 void *plat_params_from_bl2)
68{
69 static console_ls_16550_t console;
70
71 /* Initialize the console to provide early debug support */
72 console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK,
73 LS_TF_UART_BAUDRATE, &console);
74#if RESET_TO_BL31
75 /* There are no parameters from BL2 if BL31 is a reset vector */
76 assert(from_bl2 == NULL);
77 assert(plat_params_from_bl2 == NULL);
78
79#ifdef BL32_BASE
80 /* Populate entry point information for BL32 */
81 SET_PARAM_HEAD(&bl32_image_ep_info,
82 PARAM_EP,
83 VERSION_1,
84 0);
85 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
86 bl32_image_ep_info.pc = BL32_BASE;
87 bl32_image_ep_info.spsr = ls_get_spsr_for_bl32_entry();
88#endif /* BL32_BASE */
89
90 /* Populate entry point information for BL33 */
91 SET_PARAM_HEAD(&bl33_image_ep_info,
92 PARAM_EP,
93 VERSION_1,
94 0);
95 /*
96 * Tell BL31 where the non-trusted software image
97 * is located and the entry state information
98 */
99 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
100
101 bl33_image_ep_info.spsr = ls_get_spsr_for_bl33_entry();
102 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
103
104#else /* RESET_TO_BL31 */
105
106 /*
107 * In debug builds, we pass a special value in 'plat_params_from_bl2'
108 * to verify platform parameters from BL2 to BL31.
109 * In release builds, it's not used.
110 */
111 assert(((unsigned long long)plat_params_from_bl2) ==
112 LS_BL31_PLAT_PARAM_VAL);
113
114 /*
115 * Check params passed from BL2 should not be NULL,
116 */
117 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
118
119 assert(params_from_bl2 != NULL);
120 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
121 assert(params_from_bl2->h.version >= VERSION_2);
122
123 bl_params_node_t *bl_params = params_from_bl2->head;
124
125 /*
126 * Copy BL33 and BL32 (if present), entry point information.
127 * They are stored in Secure RAM, in BL2's address space.
128 */
129 while (bl_params) {
130 if (bl_params->image_id == BL32_IMAGE_ID)
131 bl32_image_ep_info = *bl_params->ep_info;
132
133 if (bl_params->image_id == BL33_IMAGE_ID)
134 bl33_image_ep_info = *bl_params->ep_info;
135
136 bl_params = bl_params->next_params_info;
137 }
138
139 if (bl33_image_ep_info.pc == 0)
140 panic();
141
142#endif /* RESET_TO_BL31 */
143}
144
145/*******************************************************************************
146 * Perform any BL31 platform setup common to Layerscape platforms
147 ******************************************************************************/
148void ls_bl31_platform_setup(void)
149{
150 uint32_t gicc_base, gicd_base;
151
152 NOTICE(FIRMWARE_WELCOME_STR_LS1043_BL31);
153 /* Initialize the GIC driver, cpu and distributor interfaces */
154 get_gic_offset(&gicc_base, &gicd_base);
155 ls_gic_data.gicd_base = (uintptr_t)gicd_base;
156 ls_gic_data.gicc_base = (uintptr_t)gicc_base;
157 gicv2_driver_init(&ls_gic_data);
158 gicv2_distif_init();
159 gicv2_pcpu_distif_init();
160 gicv2_cpuif_enable();
161
162#if RESET_TO_BL31
163 /*
164 * Do initial security configuration to allow DRAM/device access
165 * (if earlier BL has not already done so).
166 */
167 plat_ls_security_setup();
168
169#endif /* RESET_TO_BL31 */
170
171 /* Enable and initialize the System level generic timer */
172 mmio_write_32(LS1043_SYS_CNTCTL_BASE + CNTCR_OFF,
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100173 CNTCR_FCREQ(0U) | CNTCR_EN);
Jiafei Pan46367ad2018-03-02 07:23:30 +0000174
175 VERBOSE("Leave arm_bl31_platform_setup\n");
176}
177
178/*******************************************************************************
179 * Perform any BL31 platform runtime setup prior to BL31 exit common to Layerscape
180 * platforms
181 ******************************************************************************/
182void ls_bl31_plat_runtime_setup(void)
183{
184 static console_ls_16550_t console;
185
186 /* Initialize the runtime console */
187 console_ls_16550_register(PLAT_LS1043_UART_BASE, PLAT_LS1043_UART_CLOCK,
188 PLAT_LS1043_UART_BAUDRATE, &console);
189}
190
191void bl31_platform_setup(void)
192{
193 ls_bl31_platform_setup();
194}
195
196void bl31_plat_runtime_setup(void)
197{
198 ls_bl31_plat_runtime_setup();
199}
200
201/*******************************************************************************
202 * Perform the very early platform specific architectural setup shared between
203 * Layerscape platforms. This only does basic initialization. Later
204 * architectural setup (bl31_arch_setup()) does not do anything platform
205 * specific.
206 ******************************************************************************/
207void ls_bl31_plat_arch_setup(void)
208{
209 ls_setup_page_tables(BL31_BASE,
210 BL31_END - BL31_BASE,
211 BL_CODE_BASE,
212 BL_CODE_END,
213 BL_RO_DATA_BASE,
214 BL_RO_DATA_END
215#if USE_COHERENT_MEM
216 , BL_COHERENT_RAM_BASE,
217 BL_COHERENT_RAM_END
218#endif
219 );
220 enable_mmu_el3(0);
221}
222
223void bl31_plat_arch_setup(void)
224{
225 ls_bl31_plat_arch_setup();
226}