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Jens Wiklander52c798e2015-12-07 14:37:10 +01001/*
2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Jens Wiklander52c798e2015-12-07 14:37:10 +01005 */
6
7#include <assert.h>
8#include <bl_common.h>
Etienne Carriere84aa3a72017-11-02 12:05:12 +01009#include <gic_common.h>
Jens Wiklander52c798e2015-12-07 14:37:10 +010010#include <gicv2.h>
11#include <platform_def.h>
Jens Wiklander6335a972018-09-04 15:08:48 +020012#include <platform.h>
Jens Wiklander52c798e2015-12-07 14:37:10 +010013#include "qemu_private.h"
14
15/*
16 * The next 3 constants identify the extents of the code, RO data region and the
17 * limit of the BL3-1 image. These addresses are used by the MMU setup code and
18 * therefore they must be page-aligned. It is the responsibility of the linker
19 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
20 * refer to page-aligned addresses.
21 */
Jens Wiklander52c798e2015-12-07 14:37:10 +010022#define BL31_END (unsigned long)(&__BL31_END__)
23
24/*
Jens Wiklander52c798e2015-12-07 14:37:10 +010025 * Placeholder variables for copying the arguments that have been passed to
26 * BL3-1 from BL2.
27 */
28static entry_point_info_t bl32_image_ep_info;
29static entry_point_info_t bl33_image_ep_info;
30
31/*******************************************************************************
32 * Perform any BL3-1 early platform setup. Here is an opportunity to copy
33 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before
34 * they are lost (potentially). This needs to be done before the MMU is
35 * initialized so that the memory layout can be used while creating page
36 * tables. BL2 has flushed this information to memory, so we are guaranteed
37 * to pick up good data.
38 ******************************************************************************/
Jens Wiklandere22b91e2018-09-04 14:07:19 +020039void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
40 u_register_t arg2, u_register_t arg3)
Jens Wiklander52c798e2015-12-07 14:37:10 +010041{
42 /* Initialize the console to provide early debug support */
Michalis Pappascca6cb72018-03-04 15:43:38 +080043 qemu_console_init();
Jens Wiklander52c798e2015-12-07 14:37:10 +010044
Fu Weic2f78442017-05-27 21:21:42 +080045 /*
46 * Check params passed from BL2
47 */
Jens Wiklandere22b91e2018-09-04 14:07:19 +020048 bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
Fu Weic2f78442017-05-27 21:21:42 +080049
50 assert(params_from_bl2);
51 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
52 assert(params_from_bl2->h.version >= VERSION_2);
53
54 bl_params_node_t *bl_params = params_from_bl2->head;
55
56 /*
57 * Copy BL33 and BL32 (if present), entry point information.
58 * They are stored in Secure RAM, in BL2's address space.
59 */
60 while (bl_params) {
61 if (bl_params->image_id == BL32_IMAGE_ID)
62 bl32_image_ep_info = *bl_params->ep_info;
63
64 if (bl_params->image_id == BL33_IMAGE_ID)
65 bl33_image_ep_info = *bl_params->ep_info;
66
67 bl_params = bl_params->next_params_info;
68 }
69
70 if (!bl33_image_ep_info.pc)
71 panic();
Jens Wiklander52c798e2015-12-07 14:37:10 +010072}
73
74void bl31_plat_arch_setup(void)
75{
Michalis Pappasba861122018-02-28 14:36:03 +080076 qemu_configure_mmu_el3(BL31_BASE, (BL31_END - BL31_BASE),
77 BL_CODE_BASE, BL_CODE_END,
78 BL_RO_DATA_BASE, BL_RO_DATA_END,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +090079 BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
Jens Wiklander52c798e2015-12-07 14:37:10 +010080}
81
Etienne Carriere84aa3a72017-11-02 12:05:12 +010082/******************************************************************************
83 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
84 * interrupts.
85 *****************************************************************************/
86#define PLATFORM_G1S_PROPS(grp) \
87 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
88 grp, GIC_INTR_CFG_EDGE), \
89 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
90 grp, GIC_INTR_CFG_EDGE), \
91 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
92 grp, GIC_INTR_CFG_EDGE), \
93 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
94 grp, GIC_INTR_CFG_EDGE), \
95 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
96 grp, GIC_INTR_CFG_EDGE), \
97 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
98 grp, GIC_INTR_CFG_EDGE), \
99 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
100 grp, GIC_INTR_CFG_EDGE), \
101 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
102 grp, GIC_INTR_CFG_EDGE)
103
104#define PLATFORM_G0_PROPS(grp)
105
106static const interrupt_prop_t qemu_interrupt_props[] = {
107 PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
108 PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
Jens Wiklander52c798e2015-12-07 14:37:10 +0100109};
110
111static const struct gicv2_driver_data plat_gicv2_driver_data = {
112 .gicd_base = GICD_BASE,
113 .gicc_base = GICC_BASE,
Etienne Carriere84aa3a72017-11-02 12:05:12 +0100114 .interrupt_props = qemu_interrupt_props,
115 .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props),
Jens Wiklander52c798e2015-12-07 14:37:10 +0100116};
117
118void bl31_platform_setup(void)
119{
120 /* Initialize the gic cpu and distributor interfaces */
121 gicv2_driver_init(&plat_gicv2_driver_data);
122 gicv2_distif_init();
123 gicv2_pcpu_distif_init();
124 gicv2_cpuif_enable();
125}
126
127unsigned int plat_get_syscnt_freq2(void)
128{
129 return SYS_COUNTER_FREQ_IN_TICKS;
130}
131
132/*******************************************************************************
133 * Return a pointer to the 'entry_point_info' structure of the next image
134 * for the security state specified. BL3-3 corresponds to the non-secure
135 * image type while BL3-2 corresponds to the secure image type. A NULL
136 * pointer is returned if the image does not exist.
137 ******************************************************************************/
138entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
139{
140 entry_point_info_t *next_image_info;
141
142 assert(sec_state_is_valid(type));
143 next_image_info = (type == NON_SECURE)
144 ? &bl33_image_ep_info : &bl32_image_ep_info;
145 /*
146 * None of the images on the ARM development platforms can have 0x0
147 * as the entrypoint
148 */
149 if (next_image_info->pc)
150 return next_image_info;
151 else
152 return NULL;
153}