blob: 3b0d6ee37ea249bffd81a9c72bdcd4942b521956 [file] [log] [blame]
Rajan Vaja5529a012018-01-17 02:39:23 -08001/*
Ronak Jain325bad12021-12-21 01:39:59 -08002 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
Rajan Vaja5529a012018-01-17 02:39:23 -08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/*
8 * ZynqMP system level PM-API functions for pin control.
9 */
10
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000011#ifndef PM_API_IOCTL_H
12#define PM_API_IOCTL_H
Rajan Vaja5529a012018-01-17 02:39:23 -080013
14#include "pm_common.h"
15
Jolly Shah69fb5bf2018-02-07 16:25:41 -080016//ioctl id
17enum {
Ronak Jain26a8bb22021-06-27 22:31:20 -070018 IOCTL_GET_RPU_OPER_MODE = 0,
19 IOCTL_SET_RPU_OPER_MODE = 1,
20 IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
21 IOCTL_TCM_COMB_CONFIG = 3,
22 IOCTL_SET_TAPDELAY_BYPASS = 4,
23 IOCTL_SET_SGMII_MODE = 5,
24 IOCTL_SD_DLL_RESET = 6,
25 IOCTL_SET_SD_TAPDELAY = 7,
Rajan Vaja35116132018-01-17 02:39:25 -080026 /* Ioctl for clock driver */
Ronak Jain26a8bb22021-06-27 22:31:20 -070027 IOCTL_SET_PLL_FRAC_MODE = 8,
28 IOCTL_GET_PLL_FRAC_MODE = 9,
29 IOCTL_SET_PLL_FRAC_DATA = 10,
30 IOCTL_GET_PLL_FRAC_DATA = 11,
31 IOCTL_WRITE_GGS = 12,
32 IOCTL_READ_GGS = 13,
33 IOCTL_WRITE_PGGS = 14,
34 IOCTL_READ_PGGS = 15,
Siva Durga Prasad Paladugued1d5cb2018-09-04 17:03:25 +053035 /* IOCTL for ULPI reset */
Ronak Jain26a8bb22021-06-27 22:31:20 -070036 IOCTL_ULPI_RESET = 16,
Siva Durga Prasad Paladuguac8526f2018-09-04 17:12:51 +053037 /* Set healthy bit value */
Ronak Jain26a8bb22021-06-27 22:31:20 -070038 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
39 IOCTL_AFI = 18,
40 /* Probe counter read/write */
41 IOCTL_PROBE_COUNTER_READ = 19,
42 IOCTL_PROBE_COUNTER_WRITE = 20,
43 IOCTL_OSPI_MUX_SELECT = 21,
44 /* IOCTL for USB power request */
45 IOCTL_USB_SET_STATE = 22,
46 /* IOCTL to get last reset reason */
47 IOCTL_GET_LAST_RESET_REASON = 23,
48 /* AI engine NPI ISR clear */
49 IOCTL_AIE_ISR_CLEAR = 24,
50 /* Register SGI to ATF */
51 IOCTL_REGISTER_SGI = 25,
Rajan Vaja5529a012018-01-17 02:39:23 -080052};
53
Jolly Shah69fb5bf2018-02-07 16:25:41 -080054//RPU operation mode
55#define PM_RPU_MODE_LOCKSTEP 0U
56#define PM_RPU_MODE_SPLIT 1U
Rajan Vaja5529a012018-01-17 02:39:23 -080057
Jolly Shah69fb5bf2018-02-07 16:25:41 -080058//RPU boot mem
59#define PM_RPU_BOOTMEM_LOVEC 0U
60#define PM_RPU_BOOTMEM_HIVEC 1U
Rajan Vaja5529a012018-01-17 02:39:23 -080061
Jolly Shah69fb5bf2018-02-07 16:25:41 -080062//RPU tcm mpde
63#define PM_RPU_TCM_SPLIT 0U
64#define PM_RPU_TCM_COMB 1U
Rajan Vaja5529a012018-01-17 02:39:23 -080065
Jolly Shah69fb5bf2018-02-07 16:25:41 -080066//tap delay signal type
67#define PM_TAPDELAY_NAND_DQS_IN 0U
68#define PM_TAPDELAY_NAND_DQS_OUT 1U
69#define PM_TAPDELAY_QSPI 2U
70#define PM_TAPDELAY_MAX 3U
Rajan Vajaaea41bb2018-01-17 02:39:24 -080071
Jolly Shah69fb5bf2018-02-07 16:25:41 -080072//tap delay bypass
73#define PM_TAPDELAY_BYPASS_DISABLE 0U
74#define PM_TAPDELAY_BYPASS_ENABLE 1U
Rajan Vajaaea41bb2018-01-17 02:39:24 -080075
Jolly Shah69fb5bf2018-02-07 16:25:41 -080076//sgmii mode
77#define PM_SGMII_DISABLE 0U
78#define PM_SGMII_ENABLE 1U
Rajan Vajaaea41bb2018-01-17 02:39:24 -080079
80enum tap_delay_type {
81 PM_TAPDELAY_INPUT,
82 PM_TAPDELAY_OUTPUT,
83};
84
Jolly Shah69fb5bf2018-02-07 16:25:41 -080085//dll reset type
86#define PM_DLL_RESET_ASSERT 0U
87#define PM_DLL_RESET_RELEASE 1U
88#define PM_DLL_RESET_PULSE 2U
Rajan Vajaaea41bb2018-01-17 02:39:24 -080089
Rajan Vaja5529a012018-01-17 02:39:23 -080090enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
Venkatesh Yadav Abbarapue7c45382022-05-19 14:49:49 +053091 uint32_t ioctl_id,
92 uint32_t arg1,
93 uint32_t arg2,
94 uint32_t *value);
Ronak Jain325bad12021-12-21 01:39:59 -080095enum pm_ret_status atf_ioctl_bitmask(uint32_t *bit_mask);
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000096#endif /* PM_API_IOCTL_H */