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Loh Tien Hock59400a42019-02-04 16:17:24 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <drivers/arm/gicv2.h>
10
11#include <drivers/generic_delay_timer.h>
12#include <drivers/console.h>
13#include <drivers/ti/uart/uart_16550.h>
14#include <common/bl_common.h>
15#include <common/debug.h>
16#include <common/desc_image_load.h>
17#include <errno.h>
18#include <drivers/io/io_storage.h>
19#include <common/image_decompress.h>
20#include <plat/common/platform.h>
21#include <platform_def.h>
22#include <platform_private.h>
23#include <drivers/synopsys/dw_mmc.h>
24#include <lib/mmio.h>
25#include <lib/xlat_tables/xlat_tables.h>
26
27#include "s10_memory_controller.h"
28#include "s10_reset_manager.h"
29#include "s10_clock_manager.h"
30#include "s10_handoff.h"
31#include "s10_pinmux.h"
32#include "aarch64/stratix10_private.h"
Muhammad Hadi Asyrafi Abdul Halim2444bfa2019-03-08 19:02:33 +080033#include "include/s10_mailbox.h"
34#include "drivers/qspi/cadence_qspi.h"
Muhammad Hadi Asyrafi Abdul Halimc0d4d932019-03-19 17:59:06 +080035#include "drivers/wdt/watchdog.h"
Muhammad Hadi Asyrafi Abdul Halim2444bfa2019-03-08 19:02:33 +080036
Loh Tien Hock59400a42019-02-04 16:17:24 +080037
38const mmap_region_t plat_stratix10_mmap[] = {
Muhammad Hadi Asyrafi Abdul Halimb5ed7942019-03-07 13:17:25 +080039 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
40 MT_MEMORY | MT_RW | MT_NS),
41 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
42 MT_DEVICE | MT_RW | MT_NS),
43 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
44 MT_DEVICE | MT_RW | MT_SECURE),
Loh Tien Hock59400a42019-02-04 16:17:24 +080045 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
46 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
47 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
48 MT_DEVICE | MT_RW | MT_SECURE),
Muhammad Hadi Asyrafi Abdul Halimb5ed7942019-03-07 13:17:25 +080049 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
50 MT_DEVICE | MT_RW | MT_NS),
51 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
52 MT_DEVICE | MT_RW | MT_NS),
Loh Tien Hock59400a42019-02-04 16:17:24 +080053 {0},
54};
55
56boot_source_type boot_source;
57
58void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
59 u_register_t x2, u_register_t x4)
60{
61 static console_16550_t console;
62 handoff reverse_handoff_ptr;
63
64 generic_delay_timer_init();
65
66 if (s10_get_handoff(&reverse_handoff_ptr))
67 return;
68 config_pinmux(&reverse_handoff_ptr);
69 boot_source = reverse_handoff_ptr.boot_source;
70
71 config_clkmgr_handoff(&reverse_handoff_ptr);
72 enable_nonsecure_access();
73 deassert_peripheral_reset();
74 config_hps_hs_before_warm_reset();
75
Muhammad Hadi Asyrafi Abdul Halimc0d4d932019-03-19 17:59:06 +080076 watchdog_init(get_wdt_clk(&reverse_handoff_ptr));
77
Loh Tien Hock59400a42019-02-04 16:17:24 +080078 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
79 &console);
80
81 plat_delay_timer_init();
82 init_hard_memory_controller();
83}
84
85
86void bl2_el3_plat_arch_setup(void)
87{
88
89 struct mmc_device_info info;
90 const mmap_region_t bl_regions[] = {
91 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
92 MT_MEMORY | MT_RW | MT_SECURE),
93 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
94 MT_CODE | MT_SECURE),
95 MAP_REGION_FLAT(BL_RO_DATA_BASE,
96 BL_RO_DATA_END - BL_RO_DATA_BASE,
97 MT_RO_DATA | MT_SECURE),
98#if USE_COHERENT_MEM_BAR
99 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
100 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
101 MT_DEVICE | MT_RW | MT_SECURE),
102#endif
103 {0},
104 };
105
106 setup_page_tables(bl_regions, plat_stratix10_mmap);
107
108 enable_mmu_el3(0);
109
Loh Tien Hock59400a42019-02-04 16:17:24 +0800110 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000);
111
112 info.mmc_dev_type = MMC_IS_SD;
Tien Hock, Lohb978c082019-03-08 09:26:24 +0800113 info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
Loh Tien Hock59400a42019-02-04 16:17:24 +0800114
115 switch (boot_source) {
116 case BOOT_SOURCE_SDMMC:
117 dw_mmc_init(&params, &info);
Muhammad Hadi Asyrafi Abdul Halim2444bfa2019-03-08 19:02:33 +0800118 stratix10_io_setup(boot_source);
119 break;
120
121 case BOOT_SOURCE_QSPI:
122 mailbox_set_qspi_open();
123 mailbox_set_qspi_direct();
124 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
125 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
126 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
127 stratix10_io_setup(boot_source);
Loh Tien Hock59400a42019-02-04 16:17:24 +0800128 break;
Muhammad Hadi Asyrafi Abdul Halim2444bfa2019-03-08 19:02:33 +0800129
Loh Tien Hock59400a42019-02-04 16:17:24 +0800130 default:
131 ERROR("Unsupported boot source\n");
132 panic();
133 break;
134 }
135}
136
137uint32_t get_spsr_for_bl33_entry(void)
138{
139 unsigned long el_status;
140 unsigned int mode;
141 uint32_t spsr;
142
143 /* Figure out what mode we enter the non-secure world in */
144 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
145 el_status &= ID_AA64PFR0_ELX_MASK;
146
147 mode = (el_status) ? MODE_EL2 : MODE_EL1;
148
149 /*
150 * TODO: Consider the possibility of specifying the SPSR in
151 * the FIP ToC and allowing the platform to have a say as
152 * well.
153 */
154 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
155 return spsr;
156}
157
158
159int bl2_plat_handle_post_image_load(unsigned int image_id)
160{
161 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
162
163 switch (image_id) {
164 case BL33_IMAGE_ID:
165 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
166 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
167 break;
168 default:
169 break;
170 }
171
172 return 0;
173}
174
175/*******************************************************************************
176 * Perform any BL3-1 platform setup code
177 ******************************************************************************/
178void bl2_platform_setup(void)
179{
180}
181