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Haojian Zhuang602362d2017-06-01 12:15:14 +08001#
Masahiro Yamada4d156802018-01-26 11:42:01 +09002# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang602362d2017-06-01 12:15:14 +08003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Victor Chong2d9a42d2017-08-17 15:21:10 +09007# Enable version2 of image loading
8LOAD_IMAGE_V2 := 1
9
Haojian Zhuang1b4b4122018-01-25 16:13:05 +080010# Non-TF Boot ROM
11BL2_AT_EL3 := 1
12
Victor Chong91287682017-05-28 00:14:37 +090013# On Hikey960, the TSP can execute from TZC secure area in DRAM.
Victor Chong4d64c2b2018-02-01 00:37:49 +090014HIKEY960_TSP_RAM_LOCATION ?= dram
Victor Chong91287682017-05-28 00:14:37 +090015ifeq (${HIKEY960_TSP_RAM_LOCATION}, dram)
16 HIKEY960_TSP_RAM_LOCATION_ID = HIKEY960_DRAM_ID
17else ifeq (${HIKEY960_TSP_RAM_LOCATION}, sram)
Victor Chong4d64c2b2018-02-01 00:37:49 +090018 HIKEY960_TSP_RAM_LOCATION_ID = HIKEY960_SRAM_ID
Victor Chong91287682017-05-28 00:14:37 +090019else
20 $(error "Currently unsupported HIKEY960_TSP_RAM_LOCATION value")
21endif
22
Haojian Zhuang602362d2017-06-01 12:15:14 +080023CRASH_CONSOLE_BASE := PL011_UART6_BASE
24COLD_BOOT_SINGLE_CPU := 1
25PROGRAMMABLE_RESET_ADDRESS := 1
David Cunadoc5b0c0f2017-10-31 23:19:21 +000026ENABLE_SVE_FOR_NS := 0
Haojian Zhuang602362d2017-06-01 12:15:14 +080027
28# Process flags
Victor Chong91287682017-05-28 00:14:37 +090029$(eval $(call add_define,HIKEY960_TSP_RAM_LOCATION_ID))
Haojian Zhuang602362d2017-06-01 12:15:14 +080030$(eval $(call add_define,CRASH_CONSOLE_BASE))
31
Victor Chong7d787f52017-08-16 13:53:56 +090032# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
33# in the FIP if the platform requires.
34ifneq ($(BL32_EXTRA1),)
Masahiro Yamada9c5ca522018-01-26 11:42:01 +090035$(eval $(call TOOL_ADD_IMG,bl32_extra1,--tos-fw-extra1))
Victor Chong7d787f52017-08-16 13:53:56 +090036endif
37ifneq ($(BL32_EXTRA2),)
Masahiro Yamada9c5ca522018-01-26 11:42:01 +090038$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2))
Victor Chong7d787f52017-08-16 13:53:56 +090039endif
40
Haojian Zhuang602362d2017-06-01 12:15:14 +080041ENABLE_PLAT_COMPAT := 0
42
43USE_COHERENT_MEM := 1
44
45PLAT_INCLUDES := -Iinclude/common/tbbr \
46 -Iplat/hisilicon/hikey960/include
47
48PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
49 drivers/delay_timer/delay_timer.c \
50 drivers/delay_timer/generic_delay_timer.c \
51 lib/aarch64/xlat_tables.c \
52 plat/hisilicon/hikey960/aarch64/hikey960_common.c \
53 plat/hisilicon/hikey960/hikey960_boardid.c
54
55HIKEY960_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
56 drivers/arm/gic/v2/gicv2_main.c \
57 drivers/arm/gic/v2/gicv2_helpers.c \
58 plat/common/plat_gicv2.c
59
60BL1_SOURCES += bl1/tbbr/tbbr_img_desc.c \
61 drivers/io/io_block.c \
62 drivers/io/io_fip.c \
63 drivers/io/io_storage.c \
64 drivers/synopsys/ufs/dw_ufs.c \
65 drivers/ufs/ufs.c \
66 lib/cpus/aarch64/cortex_a53.S \
67 plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
Haojian Zhuangd82e29d2018-03-05 13:20:33 +080068 plat/hisilicon/hikey960/hikey960_bl1_setup.c \
69 plat/hisilicon/hikey960/hikey960_bl_common.c \
Haojian Zhuang602362d2017-06-01 12:15:14 +080070 plat/hisilicon/hikey960/hikey960_io_storage.c \
71 ${HIKEY960_GIC_SOURCES}
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080072
Haojian Zhuanga94d75d2018-01-29 12:45:28 +080073BL2_SOURCES += common/desc_image_load.c \
74 drivers/io/io_block.c \
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080075 drivers/io/io_fip.c \
76 drivers/io/io_storage.c \
Haojian Zhuang1b4b4122018-01-25 16:13:05 +080077 drivers/synopsys/ufs/dw_ufs.c \
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080078 drivers/ufs/ufs.c \
Haojian Zhuang1b4b4122018-01-25 16:13:05 +080079 lib/cpus/aarch64/cortex_a53.S \
80 plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
Haojian Zhuanga94d75d2018-01-29 12:45:28 +080081 plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c \
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080082 plat/hisilicon/hikey960/hikey960_bl2_setup.c \
Haojian Zhuangd82e29d2018-03-05 13:20:33 +080083 plat/hisilicon/hikey960/hikey960_bl_common.c \
Haojian Zhuanga94d75d2018-01-29 12:45:28 +080084 plat/hisilicon/hikey960/hikey960_image_load.c \
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080085 plat/hisilicon/hikey960/hikey960_io_storage.c \
86 plat/hisilicon/hikey960/hikey960_mcu_load.c
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080087
Victor Chong7d787f52017-08-16 13:53:56 +090088ifeq (${SPD},opteed)
89BL2_SOURCES += lib/optee/optee_utils.c
90endif
Victor Chong2d9a42d2017-08-17 15:21:10 +090091
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080092BL31_SOURCES += drivers/arm/cci/cci.c \
93 lib/cpus/aarch64/cortex_a53.S \
94 lib/cpus/aarch64/cortex_a72.S \
95 lib/cpus/aarch64/cortex_a73.S \
96 plat/common/aarch64/plat_psci_common.c \
97 plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
98 plat/hisilicon/hikey960/hikey960_bl31_setup.c \
99 plat/hisilicon/hikey960/hikey960_pm.c \
100 plat/hisilicon/hikey960/hikey960_topology.c \
101 plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c \
102 plat/hisilicon/hikey960/drivers/ipc/hisi_ipc.c \
103 ${HIKEY960_GIC_SOURCES}
Victor Chongcb27a352017-07-12 01:07:29 +0900104
105# Enable workarounds for selected Cortex-A53 errata.
106ERRATA_A53_836870 := 1
107ERRATA_A53_843419 := 1
108ERRATA_A53_855873 := 1
Leo Yan453940d2017-11-22 17:10:39 +0800109
110FIP_ALIGN := 512