blob: 71e862fa51e4b7a37b5cd3e0c3866e0285288ccd [file] [log] [blame]
Loh Tien Hock59400a42019-02-04 16:17:24 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <drivers/arm/gicv2.h>
10
11#include <drivers/generic_delay_timer.h>
12#include <drivers/console.h>
13#include <drivers/ti/uart/uart_16550.h>
14#include <common/bl_common.h>
15#include <common/debug.h>
16#include <common/desc_image_load.h>
17#include <errno.h>
18#include <drivers/io/io_storage.h>
19#include <common/image_decompress.h>
20#include <plat/common/platform.h>
21#include <platform_def.h>
22#include <platform_private.h>
23#include <drivers/synopsys/dw_mmc.h>
24#include <lib/mmio.h>
25#include <lib/xlat_tables/xlat_tables.h>
26
27#include "s10_memory_controller.h"
28#include "s10_reset_manager.h"
29#include "s10_clock_manager.h"
30#include "s10_handoff.h"
31#include "s10_pinmux.h"
32#include "aarch64/stratix10_private.h"
33
34const mmap_region_t plat_stratix10_mmap[] = {
Muhammad Hadi Asyrafi Abdul Halimb5ed7942019-03-07 13:17:25 +080035 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
36 MT_MEMORY | MT_RW | MT_NS),
37 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
38 MT_DEVICE | MT_RW | MT_NS),
39 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
40 MT_DEVICE | MT_RW | MT_SECURE),
Loh Tien Hock59400a42019-02-04 16:17:24 +080041 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
42 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
43 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
44 MT_DEVICE | MT_RW | MT_SECURE),
Muhammad Hadi Asyrafi Abdul Halimb5ed7942019-03-07 13:17:25 +080045 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
46 MT_DEVICE | MT_RW | MT_NS),
47 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
48 MT_DEVICE | MT_RW | MT_NS),
Loh Tien Hock59400a42019-02-04 16:17:24 +080049 {0},
50};
51
52boot_source_type boot_source;
53
54void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
55 u_register_t x2, u_register_t x4)
56{
57 static console_16550_t console;
58 handoff reverse_handoff_ptr;
59
60 generic_delay_timer_init();
61
62 if (s10_get_handoff(&reverse_handoff_ptr))
63 return;
64 config_pinmux(&reverse_handoff_ptr);
65 boot_source = reverse_handoff_ptr.boot_source;
66
67 config_clkmgr_handoff(&reverse_handoff_ptr);
68 enable_nonsecure_access();
69 deassert_peripheral_reset();
70 config_hps_hs_before_warm_reset();
71
72 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
73 &console);
74
75 plat_delay_timer_init();
76 init_hard_memory_controller();
77}
78
79
80void bl2_el3_plat_arch_setup(void)
81{
82
83 struct mmc_device_info info;
84 const mmap_region_t bl_regions[] = {
85 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
86 MT_MEMORY | MT_RW | MT_SECURE),
87 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
88 MT_CODE | MT_SECURE),
89 MAP_REGION_FLAT(BL_RO_DATA_BASE,
90 BL_RO_DATA_END - BL_RO_DATA_BASE,
91 MT_RO_DATA | MT_SECURE),
92#if USE_COHERENT_MEM_BAR
93 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
94 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
95 MT_DEVICE | MT_RW | MT_SECURE),
96#endif
97 {0},
98 };
99
100 setup_page_tables(bl_regions, plat_stratix10_mmap);
101
102 enable_mmu_el3(0);
103
Loh Tien Hock59400a42019-02-04 16:17:24 +0800104 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000);
105
106 info.mmc_dev_type = MMC_IS_SD;
Tien Hock, Lohb978c082019-03-08 09:26:24 +0800107 info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
Loh Tien Hock59400a42019-02-04 16:17:24 +0800108
109 switch (boot_source) {
110 case BOOT_SOURCE_SDMMC:
111 dw_mmc_init(&params, &info);
112 stratix10_io_setup();
113 break;
114 default:
115 ERROR("Unsupported boot source\n");
116 panic();
117 break;
118 }
119}
120
121uint32_t get_spsr_for_bl33_entry(void)
122{
123 unsigned long el_status;
124 unsigned int mode;
125 uint32_t spsr;
126
127 /* Figure out what mode we enter the non-secure world in */
128 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
129 el_status &= ID_AA64PFR0_ELX_MASK;
130
131 mode = (el_status) ? MODE_EL2 : MODE_EL1;
132
133 /*
134 * TODO: Consider the possibility of specifying the SPSR in
135 * the FIP ToC and allowing the platform to have a say as
136 * well.
137 */
138 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
139 return spsr;
140}
141
142
143int bl2_plat_handle_post_image_load(unsigned int image_id)
144{
145 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
146
147 switch (image_id) {
148 case BL33_IMAGE_ID:
149 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
150 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
151 break;
152 default:
153 break;
154 }
155
156 return 0;
157}
158
159/*******************************************************************************
160 * Perform any BL3-1 platform setup code
161 ******************************************************************************/
162void bl2_platform_setup(void)
163{
164}
165