blob: 203651598d0ee125d6204351d3b9f22592b438df [file] [log] [blame]
Nariman Poushinc703f902018-03-07 10:29:57 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <common/bl_common.h>
8#include <common/debug.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +00009#include <plat/arm/common/plat_arm.h>
10#include <plat/arm/soc/common/soc_css.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
Nariman Poushinc703f902018-03-07 10:29:57 +000012#include <sgm_plat_config.h>
Nariman Poushinc703f902018-03-07 10:29:57 +000013
14void bl1_early_platform_setup(void)
15{
Nariman Poushinc703f902018-03-07 10:29:57 +000016
Girish Pathak66dd23c2018-10-02 15:18:34 +010017 /* Initialize the console before anything else */
Nariman Poushinc703f902018-03-07 10:29:57 +000018 arm_bl1_early_platform_setup();
19
Girish Pathak66dd23c2018-10-02 15:18:34 +010020 /* Initialize the platform configuration structure */
21 plat_config_init();
22
Nariman Poushinc703f902018-03-07 10:29:57 +000023#if !HW_ASSISTED_COHERENCY
24 /*
25 * Initialize Interconnect for this cluster during cold boot.
26 * No need for locks as no other CPU is active.
27 */
28 plat_arm_interconnect_init();
29 /*
30 * Enable Interconnect coherency for the primary CPU's cluster.
31 */
32 plat_arm_interconnect_enter_coherency();
33#endif
34}