Marek Vasut | 3af2005 | 2019-02-25 14:57:08 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdint.h> |
| 8 | |
| 9 | #include <common/debug.h> |
| 10 | |
| 11 | #include "../qos_common.h" |
| 12 | #include "../qos_reg.h" |
| 13 | #include "qos_init_m3_v30.h" |
| 14 | |
| 15 | #define RCAR_QOS_VERSION "rev.0.1" |
| 16 | |
| 17 | #define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U) |
| 18 | #define QOSCTRL_FSS (QOS_BASE1 + 0x0048U) |
| 19 | |
| 20 | #define QOSWT_TIME_BANK0 (20000000U) //unit:ns |
| 21 | |
| 22 | #define QOSWT_WTEN_ENABLE (0x1U) |
| 23 | |
| 24 | #define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 (SL_INIT_SSLOTCLK_M3_30 - 0x5U) |
| 25 | |
| 26 | #define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U) |
| 27 | #define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U) |
| 28 | #define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT)) |
| 29 | #define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT)) |
| 30 | |
| 31 | #define QOSWT_WTSET0_REQ_SSLOT0 (5U) |
| 32 | #define WT_BASE_SUB_SLOT_NUM0 (12U) |
| 33 | #define QOSWT_WTSET0_PERIOD0_M3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U) |
| 34 | #define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U) |
| 35 | #define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U) |
| 36 | |
| 37 | #define QOSWT_WTSET1_PERIOD1_M3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U) |
| 38 | #define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U) |
| 39 | #define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U) |
| 40 | |
| 41 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 42 | |
| 43 | /* Same as M3 Ver.1.1 default setting */ |
| 44 | #if RCAR_REF_INT == RCAR_REF_DEFAULT |
| 45 | #include "qos_init_m3_v11_mstat195.h" |
| 46 | #else |
| 47 | #include "qos_init_m3_v11_mstat390.h" |
| 48 | #endif |
| 49 | |
| 50 | #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE |
| 51 | |
| 52 | /* Same as M3 Ver.1.1 default setting */ |
| 53 | #if RCAR_REF_INT == RCAR_REF_DEFAULT |
| 54 | #include "qos_init_m3_v11_qoswt195.h" |
| 55 | #else |
| 56 | #include "qos_init_m3_v11_qoswt390.h" |
| 57 | #endif |
| 58 | |
| 59 | #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ |
| 60 | #endif |
| 61 | |
| 62 | static void dbsc_setting(void) |
| 63 | { |
| 64 | uint32_t md=0; |
| 65 | |
| 66 | /* Register write enable */ |
| 67 | io_write_32(DBSC_DBSYSCNT0, 0x00001234U); |
| 68 | |
| 69 | /* BUFCAM settings */ |
| 70 | io_write_32(DBSC_DBCAM0CNF1, 0x00043218); //dbcam0cnf1 |
| 71 | io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2 |
| 72 | io_write_32(DBSC_DBCAM0CNF3, 0x00000000); //dbcam0cnf3 |
| 73 | io_write_32(DBSC_DBSCHCNT0, 0x000F0037); //dbschcnt0 |
| 74 | io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0 |
| 75 | io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0 |
| 76 | |
| 77 | md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17; |
| 78 | |
| 79 | switch (md) { |
| 80 | case 0x0: |
| 81 | /* DDR3200 */ |
| 82 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 83 | break; |
| 84 | case 0x1: //MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) |
| 85 | /* DDR2800 */ |
| 86 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 87 | break; |
| 88 | case 0x4: //MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) |
| 89 | /* DDR2400 */ |
| 90 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 91 | break; |
| 92 | default: //MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) |
| 93 | /* DDR1600 */ |
| 94 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 95 | break; |
| 96 | } |
| 97 | |
| 98 | /* QoS Settings */ |
| 99 | io_write_32(DBSC_DBSCHQOS00, 0x00000F00); |
| 100 | io_write_32(DBSC_DBSCHQOS01, 0x00000B00); |
| 101 | io_write_32(DBSC_DBSCHQOS02, 0x00000000); |
| 102 | io_write_32(DBSC_DBSCHQOS03, 0x00000000); |
| 103 | io_write_32(DBSC_DBSCHQOS40, 0x00000300); |
| 104 | io_write_32(DBSC_DBSCHQOS41, 0x000002F0); |
| 105 | io_write_32(DBSC_DBSCHQOS42, 0x00000200); |
| 106 | io_write_32(DBSC_DBSCHQOS43, 0x00000100); |
| 107 | io_write_32(DBSC_DBSCHQOS90, 0x00000100); |
| 108 | io_write_32(DBSC_DBSCHQOS91, 0x000000F0); |
| 109 | io_write_32(DBSC_DBSCHQOS92, 0x000000A0); |
| 110 | io_write_32(DBSC_DBSCHQOS93, 0x00000040); |
| 111 | io_write_32(DBSC_DBSCHQOS120, 0x00000040); |
| 112 | io_write_32(DBSC_DBSCHQOS121, 0x00000030); |
| 113 | io_write_32(DBSC_DBSCHQOS122, 0x00000020); |
| 114 | io_write_32(DBSC_DBSCHQOS123, 0x00000010); |
| 115 | io_write_32(DBSC_DBSCHQOS130, 0x00000100); |
| 116 | io_write_32(DBSC_DBSCHQOS131, 0x000000F0); |
| 117 | io_write_32(DBSC_DBSCHQOS132, 0x000000A0); |
| 118 | io_write_32(DBSC_DBSCHQOS133, 0x00000040); |
| 119 | io_write_32(DBSC_DBSCHQOS140, 0x000000C0); |
| 120 | io_write_32(DBSC_DBSCHQOS141, 0x000000B0); |
| 121 | io_write_32(DBSC_DBSCHQOS142, 0x00000080); |
| 122 | io_write_32(DBSC_DBSCHQOS143, 0x00000040); |
| 123 | io_write_32(DBSC_DBSCHQOS150, 0x00000040); |
| 124 | io_write_32(DBSC_DBSCHQOS151, 0x00000030); |
| 125 | io_write_32(DBSC_DBSCHQOS152, 0x00000020); |
| 126 | io_write_32(DBSC_DBSCHQOS153, 0x00000010); |
| 127 | |
| 128 | /* Register write protect */ |
| 129 | io_write_32(DBSC_DBSYSCNT0, 0x00000000U); |
| 130 | } |
| 131 | |
| 132 | void qos_init_m3_v30(void) |
| 133 | { |
| 134 | dbsc_setting(); |
| 135 | |
| 136 | /* DRAM Split Address mapping */ |
| 137 | #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH |
| 138 | #if RCAR_LSI == RCAR_M3 |
| 139 | #error "Don't set DRAM Split 4ch(M3)" |
| 140 | #else |
| 141 | ERROR("DRAM Split 4ch not supported.(M3)"); |
| 142 | panic(); |
| 143 | #endif |
| 144 | #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \ |
| 145 | (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) |
| 146 | NOTICE("BL2: DRAM Split is 2ch\n"); |
| 147 | io_write_32(AXI_ADSPLCR0, 0x00000000U); |
| 148 | io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT |
| 149 | | ADSPLCR0_SPLITSEL(0xFFU) |
| 150 | | ADSPLCR0_AREA(0x1DU) |
| 151 | | ADSPLCR0_SWP); |
| 152 | io_write_32(AXI_ADSPLCR2, 0x00001004U); |
| 153 | io_write_32(AXI_ADSPLCR3, 0x00000000U); |
| 154 | #else |
| 155 | NOTICE("BL2: DRAM Split is OFF\n"); |
| 156 | #endif |
| 157 | |
| 158 | #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) |
| 159 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 160 | NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); |
| 161 | #endif |
| 162 | |
| 163 | #if RCAR_REF_INT == RCAR_REF_DEFAULT |
| 164 | NOTICE("BL2: DRAM refresh interval 1.95 usec\n"); |
| 165 | #else |
| 166 | NOTICE("BL2: DRAM refresh interval 3.9 usec\n"); |
| 167 | #endif |
| 168 | |
| 169 | #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE |
| 170 | NOTICE("BL2: Periodic Write DQ Training\n"); |
| 171 | #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ |
| 172 | |
| 173 | io_write_32(QOSCTRL_RAS, 0x00000044U); |
| 174 | io_write_64(QOSCTRL_DANN, 0x0404020002020201UL); |
| 175 | io_write_32(QOSCTRL_DANT, 0x0020100AU); |
| 176 | io_write_32(QOSCTRL_FSS, 0x0000000AU); |
| 177 | io_write_32(QOSCTRL_INSFC, 0x06330001U); |
| 178 | io_write_32(QOSCTRL_EARLYR, 0x00000001U); |
| 179 | io_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */ |
| 180 | |
| 181 | /* GPU Boost Mode */ |
| 182 | io_write_32(QOSCTRL_STATGEN0, 0x00000001U); |
| 183 | |
| 184 | io_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_M3_30); |
| 185 | io_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 << 16))); |
| 186 | |
| 187 | { |
| 188 | uint32_t i; |
| 189 | |
| 190 | for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { |
| 191 | io_write_64(QOSBW_FIX_QOS_BANK0 + i*8, |
| 192 | mstat_fix[i]); |
| 193 | io_write_64(QOSBW_FIX_QOS_BANK1 + i*8, |
| 194 | mstat_fix[i]); |
| 195 | } |
| 196 | for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { |
| 197 | io_write_64(QOSBW_BE_QOS_BANK0 + i*8, |
| 198 | mstat_be[i]); |
| 199 | io_write_64(QOSBW_BE_QOS_BANK1 + i*8, |
| 200 | mstat_be[i]); |
| 201 | } |
| 202 | #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE |
| 203 | for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { |
| 204 | io_write_64(QOSWT_FIX_WTQOS_BANK0 + i*8, |
| 205 | qoswt_fix[i]); |
| 206 | io_write_64(QOSWT_FIX_WTQOS_BANK1 + i*8, |
| 207 | qoswt_fix[i]); |
| 208 | } |
| 209 | for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { |
| 210 | io_write_64(QOSWT_BE_WTQOS_BANK0 + i*8, |
| 211 | qoswt_be[i]); |
| 212 | io_write_64(QOSWT_BE_WTQOS_BANK1 + i*8, |
| 213 | qoswt_be[i]); |
| 214 | } |
| 215 | #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ |
| 216 | } |
| 217 | |
| 218 | /* RT bus Leaf setting */ |
| 219 | io_write_32(RT_ACT0, 0x00000000U); |
| 220 | io_write_32(RT_ACT1, 0x00000000U); |
| 221 | |
| 222 | /* CCI bus Leaf setting */ |
| 223 | io_write_32(CPU_ACT0, 0x00000003U); |
| 224 | io_write_32(CPU_ACT1, 0x00000003U); |
| 225 | io_write_32(CPU_ACT2, 0x00000003U); |
| 226 | io_write_32(CPU_ACT3, 0x00000003U); |
| 227 | |
| 228 | io_write_32(QOSCTRL_RAEN, 0x00000001U); |
| 229 | |
| 230 | #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE |
| 231 | /* re-write training setting */ |
| 232 | io_write_32(QOSWT_WTREF, ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN)); |
| 233 | io_write_32(QOSWT_WTSET0, ((QOSWT_WTSET0_PERIOD0_M3_30 << 16) | (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0)); |
| 234 | io_write_32(QOSWT_WTSET1, ((QOSWT_WTSET1_PERIOD1_M3_30 << 16) | (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1)); |
| 235 | |
| 236 | io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE); |
| 237 | #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ |
| 238 | |
| 239 | io_write_32(QOSCTRL_STATQC, 0x00000001U); |
| 240 | #else |
| 241 | NOTICE("BL2: QoS is None\n"); |
| 242 | |
| 243 | io_write_32(QOSCTRL_RAEN, 0x00000001U); |
| 244 | #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ |
| 245 | } |