blob: 91719867035b7109da0327784b3bd718ffffe50b [file] [log] [blame]
Konstantin Porotchkin646b5cc2018-06-07 18:48:49 +03001/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8#include <a8k_common.h>
9
10/*
11 * If bootrom is currently at BLE there's no need to include the memory
12 * maps structure at this point
13 */
14#include <mvebu_def.h>
15#ifndef IMAGE_BLE
16
17/*****************************************************************************
18 * AMB Configuration
19 *****************************************************************************
20 */
21struct addr_map_win amb_memory_map[] = {
22 /* CP0 SPI1 CS0 Direct Mode access */
23 {0xf900, 0x1000000, AMB_SPI1_CS0_ID},
24};
25
26int marvell_get_amb_memory_map(struct addr_map_win **win,
27 uint32_t *size, uintptr_t base)
28{
29 *win = amb_memory_map;
30 if (*win == NULL)
31 *size = 0;
32 else
33 *size = ARRAY_SIZE(amb_memory_map);
34
35 return 0;
36}
37#endif
38
39/*****************************************************************************
40 * IO_WIN Configuration
41 *****************************************************************************
42 */
43struct addr_map_win io_win_memory_map[] = {
44#ifndef IMAGE_BLE
45 /* MCI 0 indirect window */
46 {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
47 /* MCI 1 indirect window */
48 {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
49#endif
50};
51
52uint32_t marvell_get_io_win_gcr_target(int ap_index)
53{
54 return PIDI_TID;
55}
56
57int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
58 uint32_t *size)
59{
60 *win = io_win_memory_map;
61 if (*win == NULL)
62 *size = 0;
63 else
64 *size = ARRAY_SIZE(io_win_memory_map);
65
66 return 0;
67}
68
69#ifndef IMAGE_BLE
70/*****************************************************************************
71 * IOB Configuration
72 *****************************************************************************
73 */
74struct addr_map_win iob_memory_map[] = {
75 /* PEX1_X1 window */
76 {0x00000000f7000000, 0x1000000, PEX1_TID},
77 /* PEX2_X1 window */
78 {0x00000000f8000000, 0x1000000, PEX2_TID},
79 /* PEX0_X4 window */
80 {0x00000000f6000000, 0x1000000, PEX0_TID},
81 /* SPI1_CS0 (RUNIT) window */
82 {0x00000000f9000000, 0x1000000, RUNIT_TID},
83};
84
85int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
86 uintptr_t base)
87{
88 *win = iob_memory_map;
89 *size = ARRAY_SIZE(iob_memory_map);
90
91 return 0;
92}
93#endif
94
95/*****************************************************************************
96 * CCU Configuration
97 *****************************************************************************
98 */
99struct addr_map_win ccu_memory_map[] = { /* IO window */
100#ifdef IMAGE_BLE
101 {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
102#else
103 {0x00000000f2000000, 0xe000000, IO_0_TID},
104#endif
105};
106
107uint32_t marvell_get_ccu_gcr_target(int ap)
108{
109 return DRAM_0_TID;
110}
111
112int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win,
113 uint32_t *size)
114{
115 *win = ccu_memory_map;
116 *size = ARRAY_SIZE(ccu_memory_map);
117
118 return 0;
119}
120
121#ifdef IMAGE_BLE
122/*****************************************************************************
123 * SKIP IMAGE Configuration
124 *****************************************************************************
125 */
126#if PLAT_RECOVERY_IMAGE_ENABLE
127struct skip_image skip_im = {
128 .detection_method = GPIO,
129 .info.gpio.num = 33,
130 .info.gpio.button_state = HIGH,
131 .info.test.cp_ap = CP,
132 .info.test.cp_index = 0,
133};
134
135void *plat_marvell_get_skip_image_data(void)
136{
137 /* Return the skip_image configurations */
138 return &skip_im;
139}
140#endif
141#endif