Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 1 | /* |
Pritesh Raithatha | 45ea689 | 2017-12-18 23:00:05 -0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Varun Wadekar | 128f46a | 2019-10-24 16:06:12 -0700 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | #include <common/bl_common.h> |
| 9 | #include <mce.h> |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 10 | #include <memctrl_v2.h> |
Varun Wadekar | 128f46a | 2019-10-24 16:06:12 -0700 | [diff] [blame] | 11 | #include <tegra_mc_def.h> |
| 12 | #include <tegra_platform.h> |
Varun Wadekar | d4a698f | 2019-08-26 10:20:53 -0700 | [diff] [blame^] | 13 | #include <tegra_private.h> |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 14 | |
| 15 | /******************************************************************************* |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 16 | * Array to hold MC context for Tegra194 |
| 17 | ******************************************************************************/ |
| 18 | static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = { |
| 19 | _START_OF_TABLE_, |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 20 | mc_smmu_bypass_cfg, /* TBU settings */ |
| 21 | _END_OF_TABLE_, |
| 22 | }; |
| 23 | |
| 24 | /******************************************************************************* |
| 25 | * Handler to return the pointer to the MC's context struct |
| 26 | ******************************************************************************/ |
Varun Wadekar | d4a698f | 2019-08-26 10:20:53 -0700 | [diff] [blame^] | 27 | mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void) |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 28 | { |
| 29 | /* index of _END_OF_TABLE_ */ |
| 30 | tegra194_mc_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_mc_context) - 1U; |
| 31 | |
| 32 | return tegra194_mc_context; |
| 33 | } |
| 34 | |
| 35 | /******************************************************************************* |
Varun Wadekar | d4a698f | 2019-08-26 10:20:53 -0700 | [diff] [blame^] | 36 | * Handler to restore platform specific settings to the memory controller |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 37 | ******************************************************************************/ |
Varun Wadekar | d4a698f | 2019-08-26 10:20:53 -0700 | [diff] [blame^] | 38 | void plat_memctrl_restore(void) |
| 39 | { |
| 40 | UNUSED_FUNC_NOP(); /* do nothing */ |
| 41 | } |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 42 | |
| 43 | /******************************************************************************* |
Varun Wadekar | d4a698f | 2019-08-26 10:20:53 -0700 | [diff] [blame^] | 44 | * Handler to program platform specific settings to the memory controller |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 45 | ******************************************************************************/ |
Varun Wadekar | d4a698f | 2019-08-26 10:20:53 -0700 | [diff] [blame^] | 46 | void plat_memctrl_setup(void) |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 47 | { |
Varun Wadekar | d4a698f | 2019-08-26 10:20:53 -0700 | [diff] [blame^] | 48 | UNUSED_FUNC_NOP(); /* do nothing */ |
Steven Kao | ee93ed1 | 2017-11-14 19:12:58 +0800 | [diff] [blame] | 49 | } |
| 50 | |
| 51 | /******************************************************************************* |
| 52 | * Handler to program the scratch registers with TZDRAM settings for the |
| 53 | * resume firmware |
| 54 | ******************************************************************************/ |
| 55 | void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) |
| 56 | { |
Steven Kao | b2b4305 | 2017-11-30 11:53:29 +0800 | [diff] [blame] | 57 | uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0); |
Varun Wadekar | 22ddd8a | 2019-04-22 16:12:30 -0700 | [diff] [blame] | 58 | uint32_t phys_base_lo = (uint32_t)phys_base & 0xFFF00000; |
| 59 | uint32_t phys_base_hi = (uint32_t)(phys_base >> 32); |
Steven Kao | b2b4305 | 2017-11-30 11:53:29 +0800 | [diff] [blame] | 60 | |
Steven Kao | ee93ed1 | 2017-11-14 19:12:58 +0800 | [diff] [blame] | 61 | /* |
Steven Kao | b2b4305 | 2017-11-30 11:53:29 +0800 | [diff] [blame] | 62 | * Check TZDRAM carveout register access status. Setup TZDRAM fence |
| 63 | * only if access is enabled. |
Steven Kao | ee93ed1 | 2017-11-14 19:12:58 +0800 | [diff] [blame] | 64 | */ |
Steven Kao | b2b4305 | 2017-11-30 11:53:29 +0800 | [diff] [blame] | 65 | if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) == |
| 66 | SECURITY_CFG_WRITE_ACCESS_ENABLE) { |
Steven Kao | ee93ed1 | 2017-11-14 19:12:58 +0800 | [diff] [blame] | 67 | |
| 68 | /* |
| 69 | * Setup the Memory controller to allow only secure accesses to |
| 70 | * the TZDRAM carveout |
| 71 | */ |
| 72 | INFO("Configuring TrustZone DRAM Memory Carveout\n"); |
| 73 | |
Varun Wadekar | 22ddd8a | 2019-04-22 16:12:30 -0700 | [diff] [blame] | 74 | tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base_lo); |
| 75 | tegra_mc_write_32(MC_SECURITY_CFG3_0, phys_base_hi); |
Steven Kao | ee93ed1 | 2017-11-14 19:12:58 +0800 | [diff] [blame] | 76 | tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); |
| 77 | |
| 78 | /* |
| 79 | * MCE propagates the security configuration values across the |
| 80 | * CCPLEX. |
| 81 | */ |
| 82 | (void)mce_update_gsc_tzdram(); |
| 83 | } |
| 84 | } |