| developer | 1d69df5 | 2022-09-05 17:36:36 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef MT_CPU_PM_MBOX_H |
| 8 | #define MT_CPU_PM_MBOX_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | /* MCUPM Mbox */ |
| 13 | /* AP Write */ |
| 14 | #define MCUPM_MBOX_AP_READY (0) |
| 15 | #define MCUPM_MBOX_RESERVED_1 (1) |
| 16 | #define MCUPM_MBOX_RESERVED_2 (2) |
| 17 | #define MCUPM_MBOX_RESERVED_3 (3) |
| 18 | #define MCUPM_MBOX_PWR_CTRL_EN (4) |
| 19 | #define MCUPM_MBOX_L3_CACHE_MODE (5) |
| 20 | #define MCUPM_MBOX_BUCK_MODE (6) |
| 21 | #define MCUPM_MBOX_ARMPLL_MODE (7) |
| 22 | /* AP Read */ |
| 23 | #define MCUPM_MBOX_TASK_STA (8) |
| 24 | #define MCUPM_MBOX_RESERVED_9 (9) |
| 25 | #define MCUPM_MBOX_RESERVED_10 (10) |
| 26 | #define MCUPM_MBOX_RESERVED_11 (11) |
| 27 | #define MCUPM_MBOX_WAKEUP_CPU (12) |
| 28 | |
| 29 | /* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN (4) */ |
| 30 | #define MCUPM_MCUSYS_CTRL BIT(0) |
| 31 | #define MCUPM_BUCK_CTRL BIT(1) |
| 32 | #define MCUPM_ARMPLL_CTRL BIT(2) |
| 33 | #define MCUPM_CM_CTRL BIT(3) |
| 34 | #define MCUPM_PWR_CTRL_MASK (BIT(3) - 1) |
| 35 | |
| 36 | /* Mbox Slot: APMCU_MCUPM_MBOX_L3_CACHE_MODE (5) */ |
| 37 | #define MCUPM_L3_OFF_MODE (0) /* default */ |
| 38 | #define MCUPM_L3_DORMANT_MODE (1) |
| 39 | #define NF_MCUPM_L3_MODE (2) |
| 40 | |
| 41 | /* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE (6) */ |
| 42 | #define MCUPM_BUCK_NORMAL_MODE (0) /* default */ |
| 43 | #define MCUPM_BUCK_LP_MODE (1) |
| 44 | #define MCUPM_BUCK_OFF_MODE (2) |
| 45 | #define NF_MCUPM_BUCK_MODE (3) |
| 46 | |
| 47 | /* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE (7) */ |
| 48 | #define MCUPM_ARMPLL_ON (0) /* default */ |
| 49 | #define MCUPM_ARMPLL_GATING (1) |
| 50 | #define MCUPM_ARMPLL_OFF (2) |
| 51 | #define NF_MCUPM_ARMPLL_MODE (3) |
| 52 | |
| 53 | /* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA (9) */ |
| 54 | #define MCUPM_TASK_UNINIT (0) |
| 55 | #define MCUPM_TASK_INIT (1) |
| 56 | #define MCUPM_TASK_INIT_FINISH (2) |
| 57 | #define MCUPM_TASK_WAIT (3) |
| 58 | #define MCUPM_TASK_RUN (4) |
| 59 | #define MCUPM_TASK_PAUSE (5) |
| 60 | |
| 61 | |
| 62 | void mtk_set_mcupm_pll_mode(unsigned int mode); |
| 63 | int mtk_get_mcupm_pll_mode(void); |
| 64 | |
| 65 | void mtk_set_mcupm_buck_mode(unsigned int mode); |
| 66 | int mtk_get_mcupm_buck_mode(void); |
| 67 | |
| 68 | void mtk_set_cpu_pm_preffered_cpu(unsigned int cpuid); |
| 69 | unsigned int mtk_get_cpu_pm_preffered_cpu(void); |
| 70 | |
| 71 | enum cpupm_mbox_depd_type { |
| 72 | CPUPM_MBOX_WAIT_DEV_INIT, |
| 73 | CPUPM_MBOX_WAIT_TASK_READY, |
| 74 | }; |
| 75 | |
| 76 | int mtk_lp_depd_condition(enum cpupm_mbox_depd_type type); |
| 77 | |
| 78 | #endif /* MT_CPU_PM_MBOX_H */ |