blob: 9f49cbd26221d55ba80910221be13c688b38552b [file] [log] [blame]
Heiko Stuebner9dc28332019-03-14 22:11:34 +01001/*
2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8
9#include <arch.h>
10#include <asm_macros.S>
11#include <common/bl_common.h>
12#include <cortex_a12.h>
13#include <plat_private.h>
14#include <plat_pmu_macros.S>
15
16 .globl cpuson_entry_point
17 .globl cpuson_flags
18 .globl platform_cpu_warmboot
19 .globl plat_secondary_cold_boot_setup
20 .globl plat_report_exception
21 .globl plat_is_my_cpu_primary
22 .globl plat_my_core_pos
23 .globl plat_reset_handler
24 .globl plat_panic_handler
25
26 /*
27 * void plat_reset_handler(void);
28 *
29 * Determine the SOC type and call the appropriate reset
30 * handler.
31 *
32 */
33func plat_reset_handler
34 bx lr
35endfunc plat_reset_handler
36
37func plat_my_core_pos
38 ldcopr r0, MPIDR
39 and r1, r0, #MPIDR_CPU_MASK
40#ifdef PLAT_RK_MPIDR_CLUSTER_MASK
41 and r0, r0, #PLAT_RK_MPIDR_CLUSTER_MASK
42#else
43 and r0, r0, #MPIDR_CLUSTER_MASK
44#endif
45 add r0, r1, r0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
46 bx lr
47endfunc plat_my_core_pos
48
49 /* --------------------------------------------------------------------
50 * void plat_secondary_cold_boot_setup (void);
51 *
52 * This function performs any platform specific actions
53 * needed for a secondary cpu after a cold reset e.g
54 * mark the cpu's presence, mechanism to place it in a
55 * holding pen etc.
56 * --------------------------------------------------------------------
57 */
58func plat_secondary_cold_boot_setup
59 /* rk3288 does not do cold boot for secondary CPU */
60cb_panic:
61 b cb_panic
62endfunc plat_secondary_cold_boot_setup
63
64func plat_is_my_cpu_primary
65 ldcopr r0, MPIDR
66#ifdef PLAT_RK_MPIDR_CLUSTER_MASK
67 ldr r1, =(PLAT_RK_MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
68#else
69 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
70#endif
71 and r0, r1
72 cmp r0, #PLAT_RK_PRIMARY_CPU
73 moveq r0, #1
74 movne r0, #0
75 bx lr
76endfunc plat_is_my_cpu_primary
77
78 /* --------------------------------------------------------------------
79 * void plat_panic_handler(void)
80 * Call system reset function on panic. Set up an emergency stack so we
81 * can run C functions (it only needs to last for a few calls until we
82 * reboot anyway).
83 * --------------------------------------------------------------------
84 */
85func plat_panic_handler
86 bl plat_set_my_stack
87 b rockchip_soc_soft_reset
88endfunc plat_panic_handler
89
90 /* --------------------------------------------------------------------
91 * void platform_cpu_warmboot (void);
92 * cpus online or resume entrypoint
93 * --------------------------------------------------------------------
94 */
95func platform_cpu_warmboot _align=16
96 push { r4 - r7, lr }
97 ldcopr r0, MPIDR
98 and r5, r0, #MPIDR_CPU_MASK
99#ifdef PLAT_RK_MPIDR_CLUSTER_MASK
100 and r6, r0, #PLAT_RK_MPIDR_CLUSTER_MASK
101#else
102 and r6, r0, #MPIDR_CLUSTER_MASK
103#endif
104 mov r0, r6
105
106 func_rockchip_clst_warmboot
107 /* --------------------------------------------------------------------
108 * big cluster id is 1
109 * big cores id is from 0-3, little cores id 4-7
110 * --------------------------------------------------------------------
111 */
112 add r7, r5, r6, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
113 /* --------------------------------------------------------------------
114 * get per cpuup flag
115 * --------------------------------------------------------------------
116 */
117 ldr r4, =cpuson_flags
118 add r4, r4, r7, lsl #2
119 ldr r1, [r4]
120 /* --------------------------------------------------------------------
121 * check cpuon reason
122 * --------------------------------------------------------------------
123 */
124 cmp r1, #PMU_CPU_AUTO_PWRDN
125 beq boot_entry
126 cmp r1, #PMU_CPU_HOTPLUG
127 beq boot_entry
128 /* --------------------------------------------------------------------
129 * If the boot core cpuson_flags or cpuson_entry_point is not
130 * expection. force the core into wfe.
131 * --------------------------------------------------------------------
132 */
133wfe_loop:
134 wfe
135 b wfe_loop
136boot_entry:
137 mov r1, #0
138 str r1, [r4]
139 /* --------------------------------------------------------------------
140 * get per cpuup boot addr
141 * --------------------------------------------------------------------
142 */
143 ldr r5, =cpuson_entry_point
144 ldr r2, [r5, r7, lsl #2] /* ehem. #3 */
145 pop { r4 - r7, lr }
146
147 bx r2
148endfunc platform_cpu_warmboot
149
150 /* --------------------------------------------------------------------
151 * Per-CPU Secure entry point - resume or power up
152 * --------------------------------------------------------------------
153 */
Chris Kay33bfc5e2023-02-14 11:30:04 +0000154 .section .tzfw_coherent_mem, "a"
Heiko Stuebner9dc28332019-03-14 22:11:34 +0100155 .align 3
156cpuson_entry_point:
157 .rept PLATFORM_CORE_COUNT
158 .quad 0
159 .endr
160cpuson_flags:
161 .rept PLATFORM_CORE_COUNT
162 .word 0
163 .endr
164rockchip_clst_warmboot_data