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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Ambroise Vincent09a22e72019-05-29 14:04:16 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekarcb2dd3a2023-04-25 14:58:33 +01003 * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05304 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05306 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00008#ifndef TEGRA_PRIVATE_H
9#define TEGRA_PRIVATE_H
Varun Wadekarb316e242015-05-19 16:48:04 +053010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <platform_def.h>
Varun Wadekar8d7a02b2018-06-26 16:07:50 -070012#include <stdbool.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013
Varun Wadekara78bb1b2015-08-07 10:03:00 +053014#include <arch.h>
Varun Wadekar9f4a7d32018-10-19 11:42:28 -070015#include <arch_helpers.h>
Ambroise Vincent09a22e72019-05-29 14:04:16 +010016#include <drivers/ti/uart/uart_16550.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <lib/psci/psci.h>
18#include <lib/xlat_tables/xlat_tables_v2.h>
19
Varun Wadekar9f4a7d32018-10-19 11:42:28 -070020#include <tegra_gic.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053021
Varun Wadekar7a269e22015-06-10 14:04:32 +053022/*******************************************************************************
Steven Kaod417cea2017-06-14 14:02:23 +080023 * Implementation defined ACTLR_EL1 bit definitions
24 ******************************************************************************/
25#define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0)
26
27/*******************************************************************************
28 * Implementation defined ACTLR_EL2 bit definitions
29 ******************************************************************************/
30#define ACTLR_EL2_PMSTATE_MASK (ULL(0xF) << 0)
31
32/*******************************************************************************
Varun Wadekarb7b45752015-12-28 14:55:41 -080033 * Struct for parameters received from BL2
34 ******************************************************************************/
Varun Wadekarb316e242015-05-19 16:48:04 +053035typedef struct plat_params_from_bl2 {
Varun Wadekar6bb62462015-10-06 12:49:31 +053036 /* TZ memory size */
Varun Wadekarb316e242015-05-19 16:48:04 +053037 uint64_t tzdram_size;
Varun Wadekar6bb62462015-10-06 12:49:31 +053038 /* TZ memory base */
39 uint64_t tzdram_base;
Varun Wadekard2014c62015-10-29 10:37:28 +053040 /* UART port ID */
Varun Wadekarfda095f2019-01-02 10:48:18 -080041 int32_t uart_id;
Harvey Hsiehfbdfce12016-11-23 19:13:08 +080042 /* L2 ECC parity protection disable flag */
Varun Wadekarfda095f2019-01-02 10:48:18 -080043 int32_t l2_ecc_parity_prot_dis;
Varun Wadekar4967c3d2017-07-21 13:34:16 -070044 /* SHMEM base address for storing the boot logs */
45 uint64_t boot_profiler_shmem_base;
Varun Wadekarf07d6de2018-02-27 14:33:57 -080046 /* System Suspend Entry Firmware size */
47 uint64_t sc7entry_fw_size;
48 /* System Suspend Entry Firmware base address */
49 uint64_t sc7entry_fw_base;
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -070050 /* Enable dual execution */
51 uint8_t enable_ccplex_lock_step;
Varun Wadekarb316e242015-05-19 16:48:04 +053052} plat_params_from_bl2_t;
53
Varun Wadekardc799302015-12-28 16:36:42 -080054/*******************************************************************************
Harvey Hsiehfbdfce12016-11-23 19:13:08 +080055 * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs
56 ******************************************************************************/
57DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1)
58
59/*******************************************************************************
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +010060 * Struct describing parameters passed to bl31
61 ******************************************************************************/
62struct tegra_bl31_params {
63 param_header_t h;
64 image_info_t *bl31_image_info;
65 entry_point_info_t *bl32_ep_info;
66 image_info_t *bl32_image_info;
67 entry_point_info_t *bl33_ep_info;
68 image_info_t *bl33_image_info;
69};
70
Varun Wadekard4a698f2019-08-26 10:20:53 -070071/*******************************************************************************
72* To suppress Coverity MISRA C-2012 Rule 2.2 violations
73*******************************************************************************/
74#define UNUSED_FUNC_NOP() asm("nop")
75
Varun Wadekar254441d2015-07-23 10:07:54 +053076/* Declarations for plat_psci_handlers.c */
Anthony Zhou5d1bb052017-03-03 16:23:08 +080077int32_t tegra_soc_validate_power_state(uint32_t power_state,
Varun Wadekara78bb1b2015-08-07 10:03:00 +053078 psci_power_state_t *req_state);
Varun Wadekar254441d2015-07-23 10:07:54 +053079
Varun Wadekarb316e242015-05-19 16:48:04 +053080/* Declarations for plat_setup.c */
81const mmap_region_t *plat_get_mmio_map(void);
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070082void plat_enable_console(int32_t id);
Varun Wadekarb7b45752015-12-28 14:55:41 -080083void plat_gic_setup(void);
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +010084struct tegra_bl31_params *plat_get_bl31_params(void);
Varun Wadekard22d4ad2016-05-23 11:41:07 -070085plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
Dilan Lee1f66f3d2017-10-27 09:51:09 +080086void plat_early_platform_setup(void);
87void plat_late_platform_setup(void);
Varun Wadekar0ed62702018-06-20 14:30:59 -070088void plat_relocate_bl32_image(const image_info_t *bl32_img_info);
Varun Wadekar8d7a02b2018-06-26 16:07:50 -070089bool plat_supports_system_suspend(void);
Kalyani Chidambaram Vaidyanathane7558562020-06-15 16:48:53 -070090void plat_runtime_setup(void);
Varun Wadekarb316e242015-05-19 16:48:04 +053091
92/* Declarations for plat_secondary.c */
93void plat_secondary_setup(void);
Anthony Zhoufaad3462017-03-21 15:50:09 +080094int32_t plat_lock_cpu_vectors(void);
Varun Wadekarb316e242015-05-19 16:48:04 +053095
Varun Wadekardc799302015-12-28 16:36:42 -080096/* Declarations for tegra_fiq_glue.c */
97void tegra_fiq_handler_setup(void);
David Pu70f65972019-03-18 15:14:49 -070098int32_t tegra_fiq_get_intr_context(void);
Varun Wadekardc799302015-12-28 16:36:42 -080099void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint);
100
Varun Wadekarcb2dd3a2023-04-25 14:58:33 +0100101/* Declarations for tegra_helpers.S */
102bool plat_is_my_cpu_primary(void);
103
Varun Wadekarb316e242015-05-19 16:48:04 +0530104/* Declarations for tegra_security.c */
105void tegra_security_setup(void);
106void tegra_security_setup_videomem(uintptr_t base, uint64_t size);
107
108/* Declarations for tegra_pm.c */
109void tegra_pm_system_suspend_entry(void);
110void tegra_pm_system_suspend_exit(void);
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800111int32_t tegra_system_suspended(void);
Varun Wadekarb3421ce2017-12-27 18:10:12 -0800112int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state);
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800113int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state);
114int32_t tegra_soc_pwr_domain_on(u_register_t mpidr);
Varun Wadekarcb2dd3a2023-04-25 14:58:33 +0100115int32_t tegra_soc_pwr_domain_off_early(const psci_power_state_t *target_state);
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800116int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state);
117int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state);
118int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state);
Varun Wadekarb5b15b22018-05-17 10:10:25 -0700119int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state);
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800120int32_t tegra_soc_prepare_system_reset(void);
121__dead2 void tegra_soc_prepare_system_off(void);
122plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
123 const plat_local_state_t *states,
124 uint32_t ncpu);
Varun Wadekarb316e242015-05-19 16:48:04 +0530125
126/* Declarations for tegraXXX_pm.c */
127int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl);
128int tegra_prepare_cpu_on_finish(unsigned long mpidr);
129
130/* Declarations for tegra_bl31_setup.c */
131plat_params_from_bl2_t *bl31_get_plat_params(void);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800132int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
Varun Wadekarb316e242015-05-19 16:48:04 +0530133
Varun Wadekarbc74fec2015-07-16 15:47:03 +0530134/* Declarations for tegra_delay_timer.c */
135void tegra_delay_timer_init(void);
136
Varun Wadekar93bed2a2016-03-18 13:07:33 -0700137void tegra_secure_entrypoint(void);
Varun Wadekar93bed2a2016-03-18 13:07:33 -0700138
Anthony Zhoue5bd3452017-03-01 12:47:37 +0800139/* Declarations for tegra_sip_calls.c */
140uintptr_t tegra_sip_handler(uint32_t smc_fid,
141 u_register_t x1,
142 u_register_t x2,
143 u_register_t x3,
144 u_register_t x4,
145 void *cookie,
146 void *handle,
147 u_register_t flags);
148int plat_sip_handler(uint32_t smc_fid,
149 uint64_t x1,
150 uint64_t x2,
151 uint64_t x3,
152 uint64_t x4,
153 const void *cookie,
154 void *handle,
155 uint64_t flags);
156
Manish Pandeyd419e222023-02-13 12:39:17 +0000157#if RAS_FFH_SUPPORT
David Pu70f65972019-03-18 15:14:49 -0700158void tegra194_ras_enable(void);
David Puc3f88152019-06-07 15:30:17 -0700159void tegra194_ras_corrected_err_clear(uint64_t *cookie);
David Pu70f65972019-03-18 15:14:49 -0700160#endif
161
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000162#endif /* TEGRA_PRIVATE_H */