| Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
| 8 | #include <a8k_common.h> |
| 9 | #include <ap_setup.h> |
| 10 | #include <cp110_setup.h> |
| 11 | #include <debug.h> |
| 12 | #include <marvell_plat_priv.h> |
| 13 | #include <marvell_pm.h> |
| 14 | #include <mmio.h> |
| 15 | #include <mci.h> |
| 16 | #include <plat_marvell.h> |
| 17 | |
| 18 | #include <mss_ipc_drv.h> |
| 19 | #include <mss_mem.h> |
| 20 | |
| 21 | /* In Armada-8k family AP806/AP807, CP0 connected to PIDI |
| 22 | * and CP1 connected to IHB via MCI #0 |
| 23 | */ |
| 24 | #define MVEBU_MCI0 0 |
| 25 | |
| 26 | static _Bool pm_fw_running; |
| 27 | |
| 28 | /* Set a weak stub for platforms that don't need to configure GPIO */ |
| 29 | #pragma weak marvell_gpio_config |
| 30 | int marvell_gpio_config(void) |
| 31 | { |
| 32 | return 0; |
| 33 | } |
| 34 | |
| 35 | static void marvell_bl31_mpp_init(int cp) |
| 36 | { |
| 37 | uint32_t reg; |
| 38 | |
| 39 | /* need to do for CP#0 only */ |
| 40 | if (cp) |
| 41 | return; |
| 42 | |
| 43 | |
| 44 | /* |
| 45 | * Enable CP0 I2C MPPs (MPP: 37-38) |
| 46 | * U-Boot rely on proper MPP settings for I2C EEPROM usage |
| 47 | * (only for CP0) |
| 48 | */ |
| 49 | reg = mmio_read_32(MVEBU_CP_MPP_REGS(0, 4)); |
| 50 | mmio_write_32(MVEBU_CP_MPP_REGS(0, 4), reg | 0x2200000); |
| 51 | } |
| 52 | |
| 53 | void marvell_bl31_mss_init(void) |
| 54 | { |
| 55 | struct mss_pm_ctrl_block *mss_pm_crtl = |
| 56 | (struct mss_pm_ctrl_block *)MSS_SRAM_PM_CONTROL_BASE; |
| 57 | |
| 58 | /* Check that the image was loaded successfully */ |
| 59 | if (mss_pm_crtl->handshake != HOST_ACKNOWLEDGMENT) { |
| 60 | NOTICE("MSS PM is not supported in this build\n"); |
| 61 | return; |
| 62 | } |
| 63 | |
| 64 | /* If we got here it means that the PM firmware is running */ |
| 65 | pm_fw_running = 1; |
| 66 | |
| 67 | INFO("MSS IPC init\n"); |
| 68 | |
| 69 | if (mss_pm_crtl->ipc_state == IPC_INITIALIZED) |
| 70 | mv_pm_ipc_init(mss_pm_crtl->ipc_base_address | MVEBU_REGS_BASE); |
| 71 | } |
| 72 | |
| 73 | _Bool is_pm_fw_running(void) |
| 74 | { |
| 75 | return pm_fw_running; |
| 76 | } |
| 77 | |
| 78 | /* This function overruns the same function in marvell_bl31_setup.c */ |
| 79 | void bl31_plat_arch_setup(void) |
| 80 | { |
| 81 | int cp; |
| 82 | uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; |
| 83 | |
| 84 | /* initialize the timer for mdelay/udelay functionality */ |
| 85 | plat_delay_timer_init(); |
| 86 | |
| 87 | /* configure apn806 */ |
| 88 | ap_init(); |
| 89 | |
| 90 | /* In marvell_bl31_plat_arch_setup, el3 mmu is configured. |
| 91 | * el3 mmu configuration MUST be called after apn806_init, if not, |
| 92 | * this will cause an hang in init_io_win |
| 93 | * (after setting the IO windows GCR values). |
| 94 | */ |
| 95 | if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM || |
| 96 | mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) |
| 97 | marvell_bl31_plat_arch_setup(); |
| 98 | |
| 99 | for (cp = 0; cp < CP_COUNT; cp++) { |
| 100 | /* configure cp110 for CP0*/ |
| 101 | if (cp == 1) |
| 102 | mci_initialize(MVEBU_MCI0); |
| 103 | |
| 104 | /* initialize MCI & CP1 */ |
| 105 | cp110_init(MVEBU_CP_REGS_BASE(cp), |
| 106 | STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP)); |
| 107 | |
| 108 | /* Should be called only after setting IOB windows */ |
| 109 | marvell_bl31_mpp_init(cp); |
| 110 | } |
| 111 | |
| 112 | /* initialize IPC between MSS and ATF */ |
| 113 | if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM || |
| 114 | mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) |
| 115 | marvell_bl31_mss_init(); |
| 116 | |
| 117 | /* Configure GPIO */ |
| 118 | marvell_gpio_config(); |
| 119 | } |