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git01.mediatek.com / filogic / atf / d3e1a1d13db1ec5daf0b9922809012348374cadf / . / plat / rockchip / rk3368 / drivers / ddr / ddr_rk3368.c
blob: cb89575c991986dcfa7b38da5b14f3c0885a54f7 [file] [log] [blame]
Tony Xief6118cc2016-01-15 17:17:32 +0800[diff] [blame]1/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
18 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <mmio.h>
28#include <ddr_rk3368.h>
29#include <debug.h>
30#include <stdint.h>
31#include <string.h>
32#include <platform_def.h>
33#include <pmu.h>
34#include <rk3368_def.h>
35#include <soc.h>
36
37/* GRF_SOC_STATUS0 */
38#define DPLL_LOCK (0x1 << 2)
39
40/* GRF_DDRC0_CON0 */
41#define GRF_DDR_16BIT_EN (((0x1 << 3) << 16) | (0x1 << 3))
42#define GRF_DDR_32BIT_EN (((0x1 << 3) << 16) | (0x0 << 3))
43#define GRF_MOBILE_DDR_EN (((0x1 << 4) << 16) | (0x1 << 4))
44#define GRF_MOBILE_DDR_DISB (((0x1 << 4) << 16) | (0x0 << 4))
45#define GRF_DDR3_EN (((0x1 << 2) << 16) | (0x1 << 2))
46#define GRF_LPDDR2_3_EN (((0x1 << 2) << 16) | (0x0 << 2))
47
48/* PMUGRF_SOC_CON0 */
49#define ddrphy_bufferen_io_en(n) ((0x1 << (9 + 16)) | (n << 9))
50#define ddrphy_bufferen_core_en(n) ((0x1 << (8 + 16)) | (n << 8))
51
52struct PCTRL_TIMING_TAG {
53 uint32_t ddrfreq;
54 uint32_t TOGCNT1U;
55 uint32_t TINIT;
56 uint32_t TRSTH;
57 uint32_t TOGCNT100N;
58 uint32_t TREFI;
59 uint32_t TMRD;
60 uint32_t TRFC;
61 uint32_t TRP;
62 uint32_t TRTW;
63 uint32_t TAL;
64 uint32_t TCL;
65 uint32_t TCWL;
66 uint32_t TRAS;
67 uint32_t TRC;
68 uint32_t TRCD;
69 uint32_t TRRD;
70 uint32_t TRTP;
71 uint32_t TWR;
72 uint32_t TWTR;
73 uint32_t TEXSR;
74 uint32_t TXP;
75 uint32_t TXPDLL;
76 uint32_t TZQCS;
77 uint32_t TZQCSI;
78 uint32_t TDQS;
79 uint32_t TCKSRE;
80 uint32_t TCKSRX;
81 uint32_t TCKE;
82 uint32_t TMOD;
83 uint32_t TRSTL;
84 uint32_t TZQCL;
85 uint32_t TMRR;
86 uint32_t TCKESR;
87 uint32_t TDPD;
88 uint32_t TREFI_MEM_DDR3;
89};
90
91struct MSCH_SAVE_REG_TAG {
92 uint32_t ddrconf;
93 uint32_t ddrtiming;
94 uint32_t ddrmode;
95 uint32_t readlatency;
96 uint32_t activate;
97 uint32_t devtodev;
98};
99
100/* ddr suspend need save reg */
101struct PCTL_SAVE_REG_TAG {
102 uint32_t SCFG;
103 uint32_t CMDTSTATEN;
104 uint32_t MCFG1;
105 uint32_t MCFG;
106 uint32_t PPCFG;
107 struct PCTRL_TIMING_TAG pctl_timing;
108 /* DFI Control Registers */
109 uint32_t DFITCTRLDELAY;
110 uint32_t DFIODTCFG;
111 uint32_t DFIODTCFG1;
112 uint32_t DFIODTRANKMAP;
113 /* DFI Write Data Registers */
114 uint32_t DFITPHYWRDATA;
115 uint32_t DFITPHYWRLAT;
116 uint32_t DFITPHYWRDATALAT;
117 /* DFI Read Data Registers */
118 uint32_t DFITRDDATAEN;
119 uint32_t DFITPHYRDLAT;
120 /* DFI Update Registers */
121 uint32_t DFITPHYUPDTYPE0;
122 uint32_t DFITPHYUPDTYPE1;
123 uint32_t DFITPHYUPDTYPE2;
124 uint32_t DFITPHYUPDTYPE3;
125 uint32_t DFITCTRLUPDMIN;
126 uint32_t DFITCTRLUPDMAX;
127 uint32_t DFITCTRLUPDDLY;
128 uint32_t DFIUPDCFG;
129 uint32_t DFITREFMSKI;
130 uint32_t DFITCTRLUPDI;
131 /* DFI Status Registers */
132 uint32_t DFISTCFG0;
133 uint32_t DFISTCFG1;
134 uint32_t DFITDRAMCLKEN;
135 uint32_t DFITDRAMCLKDIS;
136 uint32_t DFISTCFG2;
137 /* DFI Low Power Register */
138 uint32_t DFILPCFG0;
139};
140
141struct DDRPHY_SAVE_REG_TAG {
142 uint32_t PHY_REG0;
143 uint32_t PHY_REG1;
144 uint32_t PHY_REGB;
145 uint32_t PHY_REGC;
146 uint32_t PHY_REG11;
147 uint32_t PHY_REG13;
148 uint32_t PHY_REG14;
149 uint32_t PHY_REG16;
150 uint32_t PHY_REG20;
151 uint32_t PHY_REG21;
152 uint32_t PHY_REG26;
153 uint32_t PHY_REG27;
154 uint32_t PHY_REG28;
155 uint32_t PHY_REG30;
156 uint32_t PHY_REG31;
157 uint32_t PHY_REG36;
158 uint32_t PHY_REG37;
159 uint32_t PHY_REG38;
160 uint32_t PHY_REG40;
161 uint32_t PHY_REG41;
162 uint32_t PHY_REG46;
163 uint32_t PHY_REG47;
164 uint32_t PHY_REG48;
165 uint32_t PHY_REG50;
166 uint32_t PHY_REG51;
167 uint32_t PHY_REG56;
168 uint32_t PHY_REG57;
169 uint32_t PHY_REG58;
170 uint32_t PHY_REGDLL;
171 uint32_t PHY_REGEC;
172 uint32_t PHY_REGED;
173 uint32_t PHY_REGEE;
174 uint32_t PHY_REGEF;
175 uint32_t PHY_REGFB;
176 uint32_t PHY_REGFC;
177 uint32_t PHY_REGFD;
178 uint32_t PHY_REGFE;
179};
180
181struct BACKUP_REG_TAG {
182 uint32_t tag;
183 uint32_t pctladdr;
184 struct PCTL_SAVE_REG_TAG pctl;
185 uint32_t phyaddr;
186 struct DDRPHY_SAVE_REG_TAG phy;
187 uint32_t nocaddr;
188 struct MSCH_SAVE_REG_TAG noc;
189 uint32_t pllselect;
190 uint32_t phypllockaddr;
191 uint32_t phyplllockmask;
192 uint32_t phyplllockval;
193 uint32_t pllpdstat;
194 uint32_t dpllmodeaddr;
195 uint32_t dpllslowmode;
196 uint32_t dpllnormalmode;
197 uint32_t dpllresetaddr;
198 uint32_t dpllreset;
199 uint32_t dplldereset;
200 uint32_t dpllconaddr;
201 uint32_t dpllcon[4];
202 uint32_t dplllockaddr;
203 uint32_t dplllockmask;
204 uint32_t dplllockval;
205 uint32_t ddrpllsrcdivaddr;
206 uint32_t ddrpllsrcdiv;
207 uint32_t retendisaddr;
208 uint32_t retendisval;
209 uint32_t grfregaddr;
210 uint32_t grfddrcreg;
211 uint32_t crupctlphysoftrstaddr;
212 uint32_t cruresetpctlphy;
213 uint32_t cruderesetphy;
214 uint32_t cruderesetpctlphy;
215 uint32_t physoftrstaddr;
216 uint32_t endtag;
217};
218
219static uint32_t ddr_get_phy_pll_freq(void)
220{
221 uint32_t ret = 0;
222 uint32_t fb_div, pre_div;
223
224 fb_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC);
225 fb_div |= (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED) & 0x1) << 8;
226
227 pre_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) & 0xff;
228 ret = 2 * 24 * fb_div / (4 * pre_div);
229
230 return ret;
231}
232
233static void ddr_copy(uint32_t *pdest, uint32_t *psrc, uint32_t words)
234{
235 uint32_t i;
236
237 for (i = 0; i < words; i++)
238 pdest[i] = psrc[i];
239}
240
241static void ddr_get_dpll_cfg(uint32_t *p)
242{
243 uint32_t nmhz, NO, NF, NR;
244
245 nmhz = ddr_get_phy_pll_freq();
246 if (nmhz <= 150)
247 NO = 6;
248 else if (nmhz <= 250)
249 NO = 4;
250 else if (nmhz <= 500)
251 NO = 2;
252 else
253 NO = 1;
254
255 NR = 1;
256 NF = 2 * nmhz * NR * NO / 24;
257
258 p[0] = SET_NR(NR) | SET_NO(NO);
259 p[1] = SET_NF(NF);
260 p[2] = SET_NB(NF / 2);
261}
262
263void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr)
264{
265 struct BACKUP_REG_TAG *p_ddr_reg = (struct BACKUP_REG_TAG *)base_addr;
266 struct PCTL_SAVE_REG_TAG *pctl_tim = &p_ddr_reg->pctl;
267
268 p_ddr_reg->tag = 0x56313031;
269 p_ddr_reg->pctladdr = DDR_PCTL_BASE;
270 p_ddr_reg->phyaddr = DDR_PHY_BASE;
271 p_ddr_reg->nocaddr = SERVICE_BUS_BASE;
272
273 /* PCTLR */
274 ddr_copy((uint32_t *)&pctl_tim->pctl_timing.TOGCNT1U,
275 (uint32_t *)(DDR_PCTL_BASE + DDR_PCTL_TOGCNT1U), 35);
276 pctl_tim->pctl_timing.TREFI |= DDR_UPD_REF_ENABLE;
277 pctl_tim->SCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_SCFG);
278 pctl_tim->CMDTSTATEN = mmio_read_32(DDR_PCTL_BASE +
279 DDR_PCTL_CMDTSTATEN);
280 pctl_tim->MCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG1);
281 pctl_tim->MCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG);
282 pctl_tim->PPCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_PPCFG);
283 pctl_tim->pctl_timing.ddrfreq = mmio_read_32(DDR_PCTL_BASE +
284 DDR_PCTL_TOGCNT1U * 2);
285 pctl_tim->DFITCTRLDELAY = mmio_read_32(DDR_PCTL_BASE +
286 DDR_PCTL_DFITCTRLDELAY);
287 pctl_tim->DFIODTCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIODTCFG);
288 pctl_tim->DFIODTCFG1 = mmio_read_32(DDR_PCTL_BASE +
289 DDR_PCTL_DFIODTCFG1);
290 pctl_tim->DFIODTRANKMAP = mmio_read_32(DDR_PCTL_BASE +
291 DDR_PCTL_DFIODTRANKMAP);
292 pctl_tim->DFITPHYWRDATA = mmio_read_32(DDR_PCTL_BASE +
293 DDR_PCTL_DFITPHYWRDATA);
294 pctl_tim->DFITPHYWRLAT = mmio_read_32(DDR_PCTL_BASE +
295 DDR_PCTL_DFITPHYWRLAT);
296 pctl_tim->DFITPHYWRDATALAT = mmio_read_32(DDR_PCTL_BASE +
297 DDR_PCTL_DFITPHYWRDATALAT);
298 pctl_tim->DFITRDDATAEN = mmio_read_32(DDR_PCTL_BASE +
299 DDR_PCTL_DFITRDDATAEN);
300 pctl_tim->DFITPHYRDLAT = mmio_read_32(DDR_PCTL_BASE +
301 DDR_PCTL_DFITPHYRDLAT);
302 pctl_tim->DFITPHYUPDTYPE0 = mmio_read_32(DDR_PCTL_BASE +
303 DDR_PCTL_DFITPHYUPDTYPE0);
304 pctl_tim->DFITPHYUPDTYPE1 = mmio_read_32(DDR_PCTL_BASE +
305 DDR_PCTL_DFITPHYUPDTYPE1);
306 pctl_tim->DFITPHYUPDTYPE2 = mmio_read_32(DDR_PCTL_BASE +
307 DDR_PCTL_DFITPHYUPDTYPE2);
308 pctl_tim->DFITPHYUPDTYPE3 = mmio_read_32(DDR_PCTL_BASE +
309 DDR_PCTL_DFITPHYUPDTYPE3);
310 pctl_tim->DFITCTRLUPDMIN = mmio_read_32(DDR_PCTL_BASE +
311 DDR_PCTL_DFITCTRLUPDMIN);
312 pctl_tim->DFITCTRLUPDMAX = mmio_read_32(DDR_PCTL_BASE +
313 DDR_PCTL_DFITCTRLUPDMAX);
314 pctl_tim->DFITCTRLUPDDLY = mmio_read_32(DDR_PCTL_BASE +
315 DDR_PCTL_DFITCTRLUPDDLY);
316
317 pctl_tim->DFIUPDCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIUPDCFG);
318 pctl_tim->DFITREFMSKI = mmio_read_32(DDR_PCTL_BASE +
319 DDR_PCTL_DFITREFMSKI);
320 pctl_tim->DFITCTRLUPDI = mmio_read_32(DDR_PCTL_BASE +
321 DDR_PCTL_DFITCTRLUPDI);
322 pctl_tim->DFISTCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG0);
323 pctl_tim->DFISTCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG1);
324 pctl_tim->DFITDRAMCLKEN = mmio_read_32(DDR_PCTL_BASE +
325 DDR_PCTL_DFITDRAMCLKEN);
326 pctl_tim->DFITDRAMCLKDIS = mmio_read_32(DDR_PCTL_BASE +
327 DDR_PCTL_DFITDRAMCLKDIS);
328 pctl_tim->DFISTCFG2 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG2);
329 pctl_tim->DFILPCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFILPCFG0);
330
331 /* PHY */
332 p_ddr_reg->phy.PHY_REG0 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG0);
333 p_ddr_reg->phy.PHY_REG1 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG1);
334 p_ddr_reg->phy.PHY_REGB = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGB);
335 p_ddr_reg->phy.PHY_REGC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGC);
336 p_ddr_reg->phy.PHY_REG11 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG11);
337 p_ddr_reg->phy.PHY_REG13 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG13);
338 p_ddr_reg->phy.PHY_REG14 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG14);
339 p_ddr_reg->phy.PHY_REG16 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG16);
340 p_ddr_reg->phy.PHY_REG20 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG20);
341 p_ddr_reg->phy.PHY_REG21 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG21);
342 p_ddr_reg->phy.PHY_REG26 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG26);
343 p_ddr_reg->phy.PHY_REG27 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG27);
344 p_ddr_reg->phy.PHY_REG28 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG28);
345 p_ddr_reg->phy.PHY_REG30 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG30);
346 p_ddr_reg->phy.PHY_REG31 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG31);
347 p_ddr_reg->phy.PHY_REG36 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG36);
348 p_ddr_reg->phy.PHY_REG37 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG37);
349 p_ddr_reg->phy.PHY_REG38 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG38);
350 p_ddr_reg->phy.PHY_REG40 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG40);
351 p_ddr_reg->phy.PHY_REG41 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG41);
352 p_ddr_reg->phy.PHY_REG46 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG46);
353 p_ddr_reg->phy.PHY_REG47 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG47);
354 p_ddr_reg->phy.PHY_REG48 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG48);
355 p_ddr_reg->phy.PHY_REG50 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG50);
356 p_ddr_reg->phy.PHY_REG51 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG51);
357 p_ddr_reg->phy.PHY_REG56 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG56);
358 p_ddr_reg->phy.PHY_REG57 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG57);
359 p_ddr_reg->phy.PHY_REG58 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG58);
360 p_ddr_reg->phy.PHY_REGDLL = mmio_read_32(DDR_PHY_BASE +
361 DDR_PHY_REGDLL);
362 p_ddr_reg->phy.PHY_REGEC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC);
363 p_ddr_reg->phy.PHY_REGED = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED);
364 p_ddr_reg->phy.PHY_REGEE = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE);
365 p_ddr_reg->phy.PHY_REGEF = 0;
366
367 if (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG2) & 0x2) {
368 p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE +
369 DDR_PHY_REG2C);
370 p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE +
371 DDR_PHY_REG3C);
372 p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE +
373 DDR_PHY_REG4C);
374 p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE +
375 DDR_PHY_REG5C);
376 } else {
377 p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE +
378 DDR_PHY_REGFB);
379 p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE +
380 DDR_PHY_REGFC);
381 p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE +
382 DDR_PHY_REGFD);
383 p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE +
384 DDR_PHY_REGFE);
385 }
386
387 /* NOC */
388 p_ddr_reg->noc.ddrconf = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRCONF);
389 p_ddr_reg->noc.ddrtiming = mmio_read_32(SERVICE_BUS_BASE +
390 MSCH_DDRTIMING);
391 p_ddr_reg->noc.ddrmode = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRMODE);
392 p_ddr_reg->noc.readlatency = mmio_read_32(SERVICE_BUS_BASE +
393 MSCH_READLATENCY);
394 p_ddr_reg->noc.activate = mmio_read_32(SERVICE_BUS_BASE +
395 MSCH_ACTIVATE);
396 p_ddr_reg->noc.devtodev = mmio_read_32(SERVICE_BUS_BASE +
397 MSCH_DEVTODEV);
398
399 p_ddr_reg->pllselect = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) * 0x1;
400 p_ddr_reg->phypllockaddr = GRF_BASE + GRF_SOC_STATUS0;
401 p_ddr_reg->phyplllockmask = GRF_DDRPHY_LOCK;
402 p_ddr_reg->phyplllockval = 0;
403
404 /* PLLPD */
405 p_ddr_reg->pllpdstat = pllpdstat;
406 /* DPLL */
407 p_ddr_reg->dpllmodeaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3);
408 /* slow mode and power on */
409 p_ddr_reg->dpllslowmode = DPLL_WORK_SLOW_MODE | DPLL_POWER_DOWN;
410 p_ddr_reg->dpllnormalmode = DPLL_WORK_NORMAL_MODE;
411 p_ddr_reg->dpllresetaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3);
412 p_ddr_reg->dpllreset = DPLL_RESET_CONTROL_NORMAL;
413 p_ddr_reg->dplldereset = DPLL_RESET_CONTROL_RESET;
414 p_ddr_reg->dpllconaddr = CRU_BASE + PLL_CONS(DPLL_ID, 0);
415
416 if (p_ddr_reg->pllselect == 0) {
417 p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE +
418 PLL_CONS(DPLL_ID, 0))
419 & 0xffff) |
420 (0xFFFF << 16);
421 p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE +
422 PLL_CONS(DPLL_ID, 1))
423 & 0xffff);
424 p_ddr_reg->dpllcon[2] = (mmio_read_32(CRU_BASE +
425 PLL_CONS(DPLL_ID, 2))
426 & 0xffff);
427 p_ddr_reg->dpllcon[3] = (mmio_read_32(CRU_BASE +
428 PLL_CONS(DPLL_ID, 3))
429 & 0xffff) |
430 (0xFFFF << 16);
431 } else {
432 ddr_get_dpll_cfg(&p_ddr_reg->dpllcon[0]);
433 }
434
435 p_ddr_reg->pllselect = 0;
436 p_ddr_reg->dplllockaddr = CRU_BASE + PLL_CONS(DPLL_ID, 1);
437 p_ddr_reg->dplllockmask = DPLL_STATUS_LOCK;
438 p_ddr_reg->dplllockval = DPLL_STATUS_LOCK;
439
440 /* SET_DDR_PLL_SRC */
441 p_ddr_reg->ddrpllsrcdivaddr = CRU_BASE + CRU_CLKSELS_CON(13);
442 p_ddr_reg->ddrpllsrcdiv = (mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(13))
443 & DDR_PLL_SRC_MASK)
444 | (DDR_PLL_SRC_MASK << 16);
445 p_ddr_reg->retendisaddr = PMU_BASE + PMU_PWRMD_COM;
446 p_ddr_reg->retendisval = PD_PERI_PWRDN_ENABLE;
447 p_ddr_reg->grfregaddr = GRF_BASE + GRF_DDRC0_CON0;
448 p_ddr_reg->grfddrcreg = (mmio_read_32(GRF_BASE + GRF_DDRC0_CON0) &
449 DDR_PLL_SRC_MASK) |
450 (DDR_PLL_SRC_MASK << 16);
451
452 /* pctl phy soft reset */
453 p_ddr_reg->crupctlphysoftrstaddr = CRU_BASE + CRU_SOFTRSTS_CON(10);
454 p_ddr_reg->cruresetpctlphy = DDRCTRL0_PSRSTN_REQ(1) |
455 DDRCTRL0_SRSTN_REQ(1) |
456 DDRPHY0_PSRSTN_REQ(1) |
457 DDRPHY0_SRSTN_REQ(1);
458 p_ddr_reg->cruderesetphy = DDRCTRL0_PSRSTN_REQ(1) |
459 DDRCTRL0_SRSTN_REQ(1) |
460 DDRPHY0_PSRSTN_REQ(0) |
461 DDRPHY0_SRSTN_REQ(0);
462
463 p_ddr_reg->cruderesetpctlphy = DDRCTRL0_PSRSTN_REQ(0) |
464 DDRCTRL0_SRSTN_REQ(0) |
465 DDRPHY0_PSRSTN_REQ(0) |
466 DDRPHY0_SRSTN_REQ(0);
467
468 p_ddr_reg->physoftrstaddr = DDR_PHY_BASE + DDR_PHY_REG0;
469
470 p_ddr_reg->endtag = 0xFFFFFFFF;
471}
472
473/*
474 * "rk3368_ddr_reg_resume_V1.05.bin" is an executable bin which is generated
475 * by ARM DS5 for resuming ddr controller. If the soc wakes up from system
476 * suspend, ddr needs to be resumed and the resuming code needs to be run in
477 * sram. But there is not a way to pointing the resuming code to the PMUSRAM
478 * when linking .o files of bl31, so we use the
479 * "rk3368_ddr_reg_resume_V1.05.bin" whose code is position-independent and
480 * it can be loaded anywhere and run.
481 */
482static __aligned(4) unsigned int ddr_reg_resume[] = {
483 #include "rk3368_ddr_reg_resume_V1.05.bin"
484};
485
486uint32_t ddr_get_resume_code_size(void)
487{
488 return sizeof(ddr_reg_resume);
489}
490
491uint32_t ddr_get_resume_data_size(void)
492{
493 return sizeof(struct BACKUP_REG_TAG);
494}
495
496uint32_t *ddr_get_resume_code_base(void)
497{
498 return (unsigned int *)ddr_reg_resume;
499}