blob: 1d79c80e75dacb90771a03b89bc4d20f3a7413e3 [file] [log] [blame]
Varun Wadekar7a269e22015-06-10 14:04:32 +05301/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
32#include <assert.h>
33#include <bl_common.h>
34#include <context_mgmt.h>
35#include <debug.h>
36#include <errno.h>
37#include <memctrl.h>
38#include <runtime_svc.h>
39#include <tegra_private.h>
40
41#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
42
43/*******************************************************************************
44 * This function is responsible for handling all SiP calls from the NS world
45 ******************************************************************************/
46uint64_t tegra_sip_handler(uint32_t smc_fid,
47 uint64_t x1,
48 uint64_t x2,
49 uint64_t x3,
50 uint64_t x4,
51 void *cookie,
52 void *handle,
53 uint64_t flags)
54{
55 uint32_t ns;
56 int err;
57
58 /* Determine which security state this SMC originated from */
59 ns = is_caller_non_secure(flags);
60 if (!ns)
61 SMC_RET1(handle, SMC_UNK);
62
63 switch (smc_fid) {
64
65 case TEGRA_SIP_NEW_VIDEOMEM_REGION:
66
67 /*
68 * Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
69 * or falls outside of the valid DRAM range
70 */
71 err = bl31_check_ns_address(x1, x2);
72 if (err)
73 SMC_RET1(handle, err);
74
75 /*
76 * Check if Video Memory is aligned to 1MB.
77 */
78 if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
79 ERROR("Unaligned Video Memory base address!\n");
80 SMC_RET1(handle, -ENOTSUP);
81 }
82
83 /* new video memory carveout settings */
84 tegra_memctrl_videomem_setup(x1, x2);
85
86 SMC_RET1(handle, 0);
87
88 default:
89 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
90 break;
91 }
92
93 SMC_RET1(handle, SMC_UNK);
94}
95
96/* Define a runtime service descriptor for fast SMC calls */
97DECLARE_RT_SVC(
98 tegra_sip_fast,
99
100 OEN_SIP_START,
101 OEN_SIP_END,
102 SMC_TYPE_FAST,
103 NULL,
104 tegra_sip_handler
105);