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git01.mediatek.com / filogic / atf / d34d7fd54b78a4b0b33ed6944a39c815cd47085f / . / include / lib / cpus / aarch64 / neoverse_v2.h
blob: 1171e9523a60318e36c54e7f438baf073bb1b45e [file] [log] [blame]
Joel Goddarda1c50ab2022-09-21 21:52:28 +0530[diff] [blame]1/*
Bipin Ravi4f9b75f2023-09-18 16:34:13 -0500[diff] [blame]2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
Joel Goddarda1c50ab2022-09-21 21:52:28 +0530[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef NEOVERSE_V2_H
8#define NEOVERSE_V2_H
9
10#define NEOVERSE_V2_MIDR U(0x410FD4F0)
11
12/* Neoverse V2 loop count for CVE-2022-23960 mitigation */
13#define NEOVERSE_V2_BHB_LOOP_COUNT U(132)
14
15/*******************************************************************************
16 * CPU Extended Control register specific definitions
17 ******************************************************************************/
18#define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4
Younghyun Parkee647e32024-05-06 21:26:38 -0700[diff] [blame]19#define NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
Joel Goddarda1c50ab2022-09-21 21:52:28 +0530[diff] [blame]20
21/*******************************************************************************
22 * CPU Power Control register specific definitions
23 ******************************************************************************/
24#define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
25#define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
Bipin Raviafcf4fe2023-10-17 19:42:15 -0500[diff] [blame]26#define NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT U(4)
27#define NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH U(3)
28#define NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT U(7)
29#define NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH U(3)
Joel Goddarda1c50ab2022-09-21 21:52:28 +0530[diff] [blame]30
Bipin Ravi4f9b75f2023-09-18 16:34:13 -0500[diff] [blame]31/*******************************************************************************
32 * CPU Extended Control register 2 specific definitions.
33 ******************************************************************************/
34#define NEOVERSE_V2_CPUECTLR2_EL1 S3_0_C15_C1_5
35#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
36#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11)
37#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
Bipin Ravi4b46c782023-10-17 18:35:55 -0500[diff] [blame]38#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0)
39#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB U(0)
40#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH U(3)
Bipin Ravi4f9b75f2023-09-18 16:34:13 -0500[diff] [blame]41
Bipin Ravi90aaf982023-09-18 17:27:29 -0500[diff] [blame]42/*******************************************************************************
43 * CPU Auxiliary Control register 2 specific definitions.
44 ******************************************************************************/
45#define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1
46#define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
47
Bipin Ravi9d46b352023-09-18 19:28:32 -0500[diff] [blame]48/*******************************************************************************
49 * CPU Auxiliary Control register 3 specific definitions.
50 ******************************************************************************/
51#define NEOVERSE_V2_CPUACTLR3_EL1 S3_0_C15_C1_2
52#define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
53
Bipin Ravia20d0612023-09-18 19:54:41 -0500[diff] [blame]54/*******************************************************************************
55 * CPU Auxiliary Control register 5 specific definitions.
56 ******************************************************************************/
57#define NEOVERSE_V2_CPUACTLR5_EL1 S3_0_C15_C8_0
58#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
59#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
60
Joel Goddarda1c50ab2022-09-21 21:52:28 +0530[diff] [blame]61#endif /* NEOVERSE_V2_H */