| Jiafei Pan | 7e20b7a | 2022-02-18 15:29:47 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2022 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | #ifndef SOC_DEFAULT_HELPER_MACROS_H |
| 7 | #define SOC_DEFAULT_HELPER_MACROS_H |
| 8 | |
| 9 | #ifdef NXP_OCRAM_TZPC_ADDR |
| 10 | #define TZPC_BLOCK_SIZE 0x1000 |
| 11 | #endif |
| 12 | |
| 13 | /* Reset block register offsets */ |
| 14 | #ifdef NXP_RESET_ADDR |
| 15 | |
| 16 | /* Register Offset */ |
| 17 | #define RST_RSTCR_OFFSET 0x0 |
| 18 | #define RST_RSTRQMR1_OFFSET 0x10 |
| 19 | #define RST_RSTRQSR1_OFFSET 0x18 |
| 20 | #define BRR_OFFSET 0x60 |
| 21 | |
| 22 | /* helper macros */ |
| 23 | #define RSTRQMR_RPTOE_MASK (1 << 19) |
| 24 | #endif /* NXP_RESET_ADDR */ |
| 25 | |
| 26 | #define PCIeRC_RN_I_NODE_ID_OFFSET 0x8 |
| 27 | #define PoS_CONTROL_REG_OFFSET 0x0 |
| 28 | #define POS_EARLY_WR_COMP_EN 0x20 |
| 29 | #define HNI_POS_EN 0x01 |
| 30 | #define POS_TERMINATE_BARRIERS 0x10 |
| 31 | #define SERIALIZE_DEV_nGnRnE_WRITES 0x200 |
| 32 | #define ENABLE_ERR_SIGNAL_TO_MN 0x4 |
| 33 | #define ENABLE_RESERVE_BIT53 0x400 |
| 34 | #define ENABLE_WUO 0x10 |
| 35 | |
| 36 | #define PORT_S0_CTRL_REG_RNI 0x010 |
| 37 | #define PORT_S1_CTRL_REG_RNI 0x110 |
| 38 | #define PORT_S2_CTRL_REG_RNI 0x210 |
| 39 | #define ENABLE_FORCE_RD_QUO 0x20 |
| 40 | #define QOS_SETTING 0x00FF000C |
| 41 | |
| 42 | /* epu register offsets and values */ |
| 43 | #define EPU_EPGCR_OFFSET 0x0 |
| 44 | #define EPU_EPIMCR10_OFFSET 0x128 |
| 45 | #define EPU_EPCTR10_OFFSET 0xa28 |
| 46 | #define EPU_EPCCR10_OFFSET 0x828 |
| 47 | #ifndef EPU_EPCCR10_VAL |
| 48 | #define EPU_EPCCR10_VAL 0xb2800000 |
| 49 | #endif |
| 50 | #define EPU_EPIMCR10_VAL 0xba000000 |
| 51 | #define EPU_EPCTR10_VAL 0x0 |
| 52 | #define EPU_EPGCR_VAL (1 << 31) |
| 53 | |
| 54 | #ifdef NXP_CCN_ADDR |
| 55 | #define NXP_CCN_HN_F_1_ADDR 0x04210000 |
| 56 | |
| 57 | #define CCN_HN_F_SAM_NODEID_MASK 0x7f |
| 58 | #define CCN_HN_F_SNP_DMN_CTL_OFFSET 0x200 |
| 59 | #define CCN_HN_F_SNP_DMN_CTL_SET_OFFSET 0x210 |
| 60 | #define CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET 0x220 |
| 61 | #define CCN_HN_F_SNP_DMN_CTL_MASK 0x80a00 |
| 62 | #define CCN_HNF_NODE_COUNT 8 |
| 63 | #define CCN_HNF_OFFSET 0x10000 |
| 64 | |
| 65 | #define SA_AUX_CTRL_REG_OFFSET 0x500 |
| 66 | #define NUM_HNI_NODE 2 |
| 67 | #define CCN_HNI_MEMORY_MAP_SIZE 0x10000 |
| 68 | |
| 69 | #define PCIeRC_RN_I_NODE_ID_OFFSET 0x8 |
| 70 | #define PoS_CONTROL_REG_OFFSET 0x0 |
| 71 | #define POS_EARLY_WR_COMP_EN 0x20 |
| 72 | #define HNI_POS_EN 0x01 |
| 73 | #define POS_TERMINATE_BARRIERS 0x10 |
| 74 | #define SERIALIZE_DEV_nGnRnE_WRITES 0x200 |
| 75 | #define ENABLE_ERR_SIGNAL_TO_MN 0x4 |
| 76 | #define ENABLE_RESERVE_BIT53 0x400 |
| 77 | #define ENABLE_WUO 0x10 |
| 78 | #endif |
| 79 | |
| 80 | /* reset register bit */ |
| 81 | #define RSTRQMR_RPTOE_MASK (1 << 19) |
| 82 | |
| 83 | /* secmon register offsets and bitfields */ |
| 84 | #define SECMON_HPCOMR_OFFSET 0x4 |
| 85 | #define SECMON_HPCOMR_NPSWAEN 0x80000000 |
| 86 | |
| 87 | /* Secure-Register-File register offsets and bit masks */ |
| 88 | #ifdef NXP_RST_ADDR |
| 89 | /* Register Offset */ |
| 90 | #define CORE_HOLD_OFFSET 0x140 |
| 91 | #endif |
| 92 | |
| 93 | #define DCFG_SBEESR2_ADDR 0x00100534 |
| 94 | #define DCFG_MBEESR2_ADDR 0x00100544 |
| 95 | /* SBEESR and MBEESR bit mask */ |
| 96 | #define OCRAM_EESR_MASK 0x00000008 |
| 97 | |
| 98 | #endif /* SOC_DEFAULT_HELPER_MACROS_H */ |