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Xing Zheng93280b72016-10-26 21:25:26 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Xing Zheng93280b72016-10-26 21:25:26 +08005 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <debug.h>
Derek Basehorec8e5c782017-02-24 14:33:03 +080010#include <delay_timer.h>
Xing Zheng93280b72016-10-26 21:25:26 +080011#include <mmio.h>
12#include <m0_ctl.h>
13#include <plat_private.h>
14#include <rk3399_def.h>
Xing Zheng22a98712017-02-24 14:56:41 +080015#include <secure.h>
Xing Zheng93280b72016-10-26 21:25:26 +080016#include <soc.h>
17
18void m0_init(void)
19{
20 /* secure config for M0 */
21 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7));
Xing Zheng22a98712017-02-24 14:56:41 +080022 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12));
Xing Zheng93280b72016-10-26 21:25:26 +080023
24 /* set the execute address for M0 */
25 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3),
26 BITS_WITH_WMASK((M0_BINCODE_BASE >> 12) & 0xffff,
27 0xffff, 0));
28 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7),
29 BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf,
30 0xf, 0));
31
Lin Huang8140b7d2016-12-30 13:53:25 +080032 /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
33 mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02);
Xing Zheng93280b72016-10-26 21:25:26 +080034
35 /*
36 * To switch the parent to xin24M and div == 1,
37 *
38 * We need to close most of the PLLs and clocks except the OSC 24MHz
39 * durning suspend, and this should be enough to supplies the ddrfreq,
40 * For the simple handle, we just keep the fixed 24MHz to supply the
41 * suspend and ddrfreq directly.
42 */
43 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0,
44 BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8));
Lin Huangb4a76762016-12-12 15:18:08 +080045
46 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5));
Xing Zheng93280b72016-10-26 21:25:26 +080047}
48
49void m0_start(void)
50{
Lin Huangb4a76762016-12-12 15:18:08 +080051 /* enable clocks for M0 */
52 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
53 BITS_WITH_WMASK(0x0, 0xf, 0));
54
Xing Zheng93280b72016-10-26 21:25:26 +080055 /* clean the PARAM_M0_DONE flag, mean that M0 will start working */
56 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0);
Derek Basehorec8e5c782017-02-24 14:33:03 +080057 dmbst();
Xing Zheng93280b72016-10-26 21:25:26 +080058
Lin Huangb4a76762016-12-12 15:18:08 +080059 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
60 BITS_WITH_WMASK(0x0, 0x4, 0));
Xing Zheng93280b72016-10-26 21:25:26 +080061
Lin Huangb4a76762016-12-12 15:18:08 +080062 udelay(5);
Xing Zheng93280b72016-10-26 21:25:26 +080063 /* start M0 */
64 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
Lin Huangb4a76762016-12-12 15:18:08 +080065 BITS_WITH_WMASK(0x0, 0x20, 0));
66 dmbst();
Xing Zheng93280b72016-10-26 21:25:26 +080067}
68
69void m0_stop(void)
70{
71 /* stop M0 */
72 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
73 BITS_WITH_WMASK(0x24, 0x24, 0));
74
75 /* disable clocks for M0 */
76 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
Lin Huangb4a76762016-12-12 15:18:08 +080077 BITS_WITH_WMASK(0xf, 0xf, 0));
Xing Zheng93280b72016-10-26 21:25:26 +080078}
79
80void m0_wait_done(void)
81{
Lin Huangb4a76762016-12-12 15:18:08 +080082 do {
Derek Basehorec8e5c782017-02-24 14:33:03 +080083 /*
84 * Don't starve the M0 for access to SRAM, so delay before
85 * reading the PARAM_M0_DONE value again.
86 */
87 udelay(5);
Xing Zheng93280b72016-10-26 21:25:26 +080088 dsb();
Lin Huangb4a76762016-12-12 15:18:08 +080089 } while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG);
90
91 /*
92 * Let the M0 settle into WFI before we leave. This is so we don't reset
93 * the M0 in a bad spot which can cause problems with the M0.
94 */
95 udelay(10);
96 dsb();
Xing Zheng93280b72016-10-26 21:25:26 +080097}