| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | # |
| 2 | # Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | # |
| 4 | # Redistribution and use in source and binary forms, with or without |
| 5 | # modification, are permitted provided that the following conditions are met: |
| 6 | # |
| 7 | # Redistributions of source code must retain the above copyright notice, this |
| 8 | # list of conditions and the following disclaimer. |
| 9 | # |
| 10 | # Redistributions in binary form must reproduce the above copyright notice, |
| 11 | # this list of conditions and the following disclaimer in the documentation |
| 12 | # and/or other materials provided with the distribution. |
| 13 | # |
| 14 | # Neither the name of ARM nor the names of its contributors may be used |
| 15 | # to endorse or promote products derived from this software without specific |
| 16 | # prior written permission. |
| 17 | # |
| 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | # POSSIBILITY OF SUCH DAMAGE. |
| 29 | # |
| 30 | |
| Varun Wadekar | d1b6150 | 2015-07-16 09:46:28 +0530 | [diff] [blame] | 31 | TZDRAM_BASE := 0xFDC00000 |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 32 | $(eval $(call add_define,TZDRAM_BASE)) |
| 33 | |
| 34 | ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1 |
| 35 | $(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT)) |
| 36 | |
| Varun Wadekar | d1b6150 | 2015-07-16 09:46:28 +0530 | [diff] [blame] | 37 | PLATFORM_CLUSTER_COUNT := 2 |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 38 | $(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) |
| 39 | |
| Varun Wadekar | d1b6150 | 2015-07-16 09:46:28 +0530 | [diff] [blame] | 40 | PLATFORM_MAX_CPUS_PER_CLUSTER := 4 |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 41 | $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) |
| 42 | |
| Varun Wadekar | 97f2490 | 2015-09-09 11:29:24 +0530 | [diff] [blame] | 43 | MAX_XLAT_TABLES := 3 |
| 44 | $(eval $(call add_define,MAX_XLAT_TABLES)) |
| 45 | |
| 46 | MAX_MMAP_REGIONS := 8 |
| 47 | $(eval $(call add_define,MAX_MMAP_REGIONS)) |
| 48 | |
| Varun Wadekar | 5f4e643 | 2015-07-21 11:53:35 +0530 | [diff] [blame] | 49 | BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ |
| 50 | lib/cpus/aarch64/cortex_a57.S \ |
| Varun Wadekar | a1176ba | 2015-08-25 17:01:06 +0530 | [diff] [blame] | 51 | ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ |
| Varun Wadekar | 7a9a285 | 2015-09-18 11:21:22 +0530 | [diff] [blame] | 52 | ${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \ |
| Varun Wadekar | 5f4e643 | 2015-07-21 11:53:35 +0530 | [diff] [blame] | 53 | ${SOC_DIR}/plat_psci_handlers.c \ |
| Varun Wadekar | cbdace1 | 2015-09-03 14:32:44 +0530 | [diff] [blame] | 54 | ${SOC_DIR}/plat_sip_calls.c \ |
| Varun Wadekar | 5f4e643 | 2015-07-21 11:53:35 +0530 | [diff] [blame] | 55 | ${SOC_DIR}/plat_setup.c \ |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 56 | ${SOC_DIR}/plat_secondary.c |
| 57 | |
| 58 | # Enable workarounds for selected Cortex-A53 erratas. |
| 59 | ERRATA_A53_826319 := 1 |
| Varun Wadekar | d1b6150 | 2015-07-16 09:46:28 +0530 | [diff] [blame] | 60 | |