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Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Tony Xief6118cc2016-01-15 17:17:32 +08005 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <bl_common.h>
10#include <cortex_a53.h>
11#include <cortex_a72.h>
12#include <plat_private.h>
13#include <platform_def.h>
Tony Xie42e113e2016-07-16 11:16:51 +080014#include <plat_pmu_macros.S>
Tony Xief6118cc2016-01-15 17:17:32 +080015
16 .globl cpuson_entry_point
17 .globl cpuson_flags
18 .globl platform_cpu_warmboot
19 .globl plat_secondary_cold_boot_setup
20 .globl plat_report_exception
21 .globl platform_is_primary_cpu
22 .globl plat_crash_console_init
23 .globl plat_crash_console_putc
24 .globl plat_my_core_pos
25 .globl plat_reset_handler
26
Tony Xief6118cc2016-01-15 17:17:32 +080027 /*
28 * void plat_reset_handler(void);
29 *
30 * Determine the SOC type and call the appropriate reset
31 * handler.
32 *
33 */
34func plat_reset_handler
Tony Xie42e113e2016-07-16 11:16:51 +080035 mrs x0, midr_el1
36 ubfx x0, x0, MIDR_PN_SHIFT, #12
37 cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
38 b.eq handler_a72
39 b handler_end
40handler_a72:
41 /*
42 * This handler does the following:
43 * Set the L2 Data RAM latency for Cortex-A72.
44 * Set the L2 Tag RAM latency to for Cortex-A72.
45 */
Varun Wadekar1384a162017-06-05 14:54:46 -070046 mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
Tony Xie42e113e2016-07-16 11:16:51 +080047 (0x1 << 5))
Varun Wadekar1384a162017-06-05 14:54:46 -070048 msr CORTEX_A72_L2CTLR_EL1, x0
Tony Xie42e113e2016-07-16 11:16:51 +080049 isb
50handler_end:
51 ret
Tony Xief6118cc2016-01-15 17:17:32 +080052endfunc plat_reset_handler
53
54func plat_my_core_pos
55 mrs x0, mpidr_el1
56 and x1, x0, #MPIDR_CPU_MASK
57 and x0, x0, #MPIDR_CLUSTER_MASK
Tony Xie42e113e2016-07-16 11:16:51 +080058 add x0, x1, x0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
Tony Xief6118cc2016-01-15 17:17:32 +080059 ret
60endfunc plat_my_core_pos
61
62 /* --------------------------------------------------------------------
63 * void plat_secondary_cold_boot_setup (void);
64 *
65 * This function performs any platform specific actions
66 * needed for a secondary cpu after a cold reset e.g
67 * mark the cpu's presence, mechanism to place it in a
68 * holding pen etc.
69 * --------------------------------------------------------------------
70 */
71func plat_secondary_cold_boot_setup
72 /* rk3368 does not do cold boot for secondary CPU */
73cb_panic:
74 b cb_panic
75endfunc plat_secondary_cold_boot_setup
76
77func platform_is_primary_cpu
78 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
79 cmp x0, #PLAT_RK_PRIMARY_CPU
80 cset x0, eq
81 ret
82endfunc platform_is_primary_cpu
83
84 /* --------------------------------------------------------------------
85 * int plat_crash_console_init(void)
86 * Function to initialize the crash console
87 * without a C Runtime to print crash report.
88 * Clobber list : x0, x1, x2
89 * --------------------------------------------------------------------
90 */
91func plat_crash_console_init
92 mov_imm x0, PLAT_RK_UART_BASE
93 mov_imm x1, PLAT_RK_UART_CLOCK
94 mov_imm x2, PLAT_RK_UART_BAUDRATE
95 b console_core_init
96endfunc plat_crash_console_init
97
98 /* --------------------------------------------------------------------
99 * int plat_crash_console_putc(void)
100 * Function to print a character on the crash
101 * console without a C Runtime.
102 * Clobber list : x1, x2
103 * --------------------------------------------------------------------
104 */
105func plat_crash_console_putc
106 mov_imm x1, PLAT_RK_UART_BASE
107 b console_core_putc
108endfunc plat_crash_console_putc
109
110 /* --------------------------------------------------------------------
111 * void platform_cpu_warmboot (void);
112 * cpus online or resume enterpoint
113 * --------------------------------------------------------------------
114 */
Caesar Wang59e41b52016-04-10 14:11:07 +0800115 .align 16
Tony Xief6118cc2016-01-15 17:17:32 +0800116func platform_cpu_warmboot
117 mrs x0, MPIDR_EL1
Tony Xie42e113e2016-07-16 11:16:51 +0800118 and x19, x0, #MPIDR_CPU_MASK
119 and x20, x0, #MPIDR_CLUSTER_MASK
120 mov x0, x20
121 func_rockchip_clst_warmboot
Tony Xief6118cc2016-01-15 17:17:32 +0800122 /* --------------------------------------------------------------------
123 * big cluster id is 1
124 * big cores id is from 0-3, little cores id 4-7
125 * --------------------------------------------------------------------
126 */
Tony Xie42e113e2016-07-16 11:16:51 +0800127 add x21, x19, x20, lsr #PLAT_RK_CLST_TO_CPUID_SHIFT
Tony Xief6118cc2016-01-15 17:17:32 +0800128 /* --------------------------------------------------------------------
129 * get per cpuup flag
130 * --------------------------------------------------------------------
131 */
132 adr x4, cpuson_flags
Tony Xie42e113e2016-07-16 11:16:51 +0800133 add x4, x4, x21, lsl #2
Tony Xief6118cc2016-01-15 17:17:32 +0800134 ldr w1, [x4]
135 /* --------------------------------------------------------------------
Tony Xief6118cc2016-01-15 17:17:32 +0800136 * check cpuon reason
137 * --------------------------------------------------------------------
138 */
Tony Xie42e113e2016-07-16 11:16:51 +0800139 cmp w1, PMU_CPU_AUTO_PWRDN
Tony Xief6118cc2016-01-15 17:17:32 +0800140 b.eq boot_entry
Tony Xie42e113e2016-07-16 11:16:51 +0800141 cmp w1, PMU_CPU_HOTPLUG
Tony Xief6118cc2016-01-15 17:17:32 +0800142 b.eq boot_entry
143 /* --------------------------------------------------------------------
144 * If the boot core cpuson_flags or cpuson_entry_point is not
145 * expection. force the core into wfe.
146 * --------------------------------------------------------------------
147 */
148wfe_loop:
149 wfe
150 b wfe_loop
151boot_entry:
Tony Xie42e113e2016-07-16 11:16:51 +0800152 str wzr, [x4]
Caesar Wang59e41b52016-04-10 14:11:07 +0800153 /* --------------------------------------------------------------------
154 * get per cpuup boot addr
155 * --------------------------------------------------------------------
156 */
157 adr x5, cpuson_entry_point
Tony Xie42e113e2016-07-16 11:16:51 +0800158 ldr x2, [x5, x21, lsl #3]
Tony Xief6118cc2016-01-15 17:17:32 +0800159 br x2
160endfunc platform_cpu_warmboot
161
162 /* --------------------------------------------------------------------
163 * Per-CPU Secure entry point - resume or power up
164 * --------------------------------------------------------------------
165 */
166 .section tzfw_coherent_mem, "a"
167 .align 3
168cpuson_entry_point:
169 .rept PLATFORM_CORE_COUNT
170 .quad 0
171 .endr
172cpuson_flags:
173 .rept PLATFORM_CORE_COUNT
Caesar Wang59e41b52016-04-10 14:11:07 +0800174 .word 0
Tony Xief6118cc2016-01-15 17:17:32 +0800175 .endr
Tony Xie42e113e2016-07-16 11:16:51 +0800176rockchip_clst_warmboot_data