blob: b7e49a278b1f41ea45eae67ab018478779814241 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#include <arch_helpers.h>
Dan Handleyfb42b122014-06-20 09:43:15 +010032#include <arm_gic.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010034#include <bakery_lock.h>
35#include <cci400.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010036#include <mmio.h>
37#include <platform.h>
Dan Handley1c54d972014-06-20 12:02:01 +010038#include <plat_config.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010039#include <platform_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010040#include <psci.h>
Dan Handley4d2e49d2014-04-11 11:52:12 +010041#include "drivers/pwrc/fvp_pwrc.h"
Dan Handleyed6ff952014-05-14 17:44:19 +010042#include "fvp_def.h"
43#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010044
45/*******************************************************************************
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +000046 * FVP handler called when an affinity instance is about to enter standby.
47 ******************************************************************************/
48int fvp_affinst_standby(unsigned int power_state)
49{
50 unsigned int target_afflvl;
51
52 /* Sanity check the requested state */
53 target_afflvl = psci_get_pstate_afflvl(power_state);
54
55 /*
56 * It's possible to enter standby only on affinity level 0 i.e. a cpu
57 * on the FVP. Ignore any other affinity level.
58 */
59 if (target_afflvl != MPIDR_AFFLVL0)
60 return PSCI_E_INVALID_PARAMS;
61
Andrew Thoelke42e75a72014-04-28 12:28:39 +010062 /*
63 * Enter standby state
64 * dsb is good practice before using wfi to enter low power states
65 */
66 dsb();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +000067 wfi();
68
69 return PSCI_E_SUCCESS;
70}
71
72/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010073 * FVP handler called when an affinity instance is about to be turned on. The
74 * level and mpidr determine the affinity instance.
75 ******************************************************************************/
76int fvp_affinst_on(unsigned long mpidr,
77 unsigned long sec_entrypoint,
78 unsigned long ns_entrypoint,
79 unsigned int afflvl,
80 unsigned int state)
81{
82 int rc = PSCI_E_SUCCESS;
83 unsigned long linear_id;
Dan Handleye2712bc2014-04-10 15:37:22 +010084 mailbox_t *fvp_mboxes;
Achin Gupta4f6ad662013-10-25 09:08:21 +010085 unsigned int psysr;
86
Achin Gupta4f6ad662013-10-25 09:08:21 +010087 /*
88 * It's possible to turn on only affinity level 0 i.e. a cpu
89 * on the FVP. Ignore any other affinity level.
90 */
91 if (afflvl != MPIDR_AFFLVL0)
92 goto exit;
93
94 /*
95 * Ensure that we do not cancel an inflight power off request
96 * for the target cpu. That would leave it in a zombie wfi.
97 * Wait for it to power off, program the jump address for the
98 * target cpu and then program the power controller to turn
99 * that cpu on
100 */
101 do {
102 psysr = fvp_pwrc_read_psysr(mpidr);
103 } while (psysr & PSYSR_AFF_L0);
104
105 linear_id = platform_get_core_pos(mpidr);
Juan Castillo48e84b32014-08-12 13:51:51 +0100106 fvp_mboxes = (mailbox_t *)MBOX_BASE;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100107 fvp_mboxes[linear_id].value = sec_entrypoint;
108 flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
109 sizeof(unsigned long));
110
111 fvp_pwrc_write_pponr(mpidr);
112
113exit:
114 return rc;
115}
116
117/*******************************************************************************
118 * FVP handler called when an affinity instance is about to be turned off. The
119 * level and mpidr determine the affinity instance. The 'state' arg. allows the
120 * platform to decide whether the cluster is being turned off and take apt
121 * actions.
122 *
Achin Gupta9c60d802014-06-26 11:12:37 +0100123 * CAUTION: There is no guarantee that caches will remain turned on across calls
124 * to this function as each affinity level is dealt with. So do not write & read
125 * global variables across calls. It will be wise to do flush a write to the
126 * global to prevent unpredictable results.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127 ******************************************************************************/
128int fvp_affinst_off(unsigned long mpidr,
129 unsigned int afflvl,
130 unsigned int state)
131{
132 int rc = PSCI_E_SUCCESS;
Dan Handleyfb42b122014-06-20 09:43:15 +0100133 unsigned int ectlr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100134
135 switch (afflvl) {
136 case MPIDR_AFFLVL1:
137 if (state == PSCI_STATE_OFF) {
138 /*
139 * Disable coherency if this cluster is to be
140 * turned off
141 */
Dan Handley1c54d972014-06-20 12:02:01 +0100142 if (get_plat_config()->flags & CONFIG_HAS_CCI)
Dan Handleybe234f92014-08-04 16:11:15 +0100143 cci_disable_cluster_coherency(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144
145 /*
146 * Program the power controller to turn the
147 * cluster off
148 */
149 fvp_pwrc_write_pcoffr(mpidr);
150
151 }
152 break;
153
154 case MPIDR_AFFLVL0:
155 if (state == PSCI_STATE_OFF) {
156
157 /*
158 * Take this cpu out of intra-cluster coherency if
159 * the FVP flavour supports the SMP bit.
160 */
Dan Handley1c54d972014-06-20 12:02:01 +0100161 if (get_plat_config()->flags & CONFIG_CPUECTLR_SMP_BIT) {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100162 ectlr = read_cpuectlr();
163 ectlr &= ~CPUECTLR_SMP_BIT;
164 write_cpuectlr(ectlr);
165 }
166
167 /*
168 * Prevent interrupts from spuriously waking up
169 * this cpu
170 */
Dan Handleyfb42b122014-06-20 09:43:15 +0100171 arm_gic_cpuif_deactivate();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100172
173 /*
174 * Program the power controller to power this
175 * cpu off
176 */
177 fvp_pwrc_write_ppoffr(mpidr);
178 }
179 break;
180
181 default:
182 assert(0);
183 }
184
185 return rc;
186}
187
188/*******************************************************************************
189 * FVP handler called when an affinity instance is about to be suspended. The
190 * level and mpidr determine the affinity instance. The 'state' arg. allows the
191 * platform to decide whether the cluster is being turned off and take apt
192 * actions.
193 *
Achin Gupta9c60d802014-06-26 11:12:37 +0100194 * CAUTION: There is no guarantee that caches will remain turned on across calls
195 * to this function as each affinity level is dealt with. So do not write & read
196 * global variables across calls. It will be wise to do flush a write to the
197 * global to prevent unpredictable results.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100198 ******************************************************************************/
199int fvp_affinst_suspend(unsigned long mpidr,
200 unsigned long sec_entrypoint,
201 unsigned long ns_entrypoint,
202 unsigned int afflvl,
203 unsigned int state)
204{
205 int rc = PSCI_E_SUCCESS;
Dan Handleyfb42b122014-06-20 09:43:15 +0100206 unsigned int ectlr;
Dan Handley1c54d972014-06-20 12:02:01 +0100207 unsigned long linear_id;
Dan Handleye2712bc2014-04-10 15:37:22 +0100208 mailbox_t *fvp_mboxes;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100209
Achin Gupta4f6ad662013-10-25 09:08:21 +0100210 switch (afflvl) {
211 case MPIDR_AFFLVL1:
212 if (state == PSCI_STATE_OFF) {
213 /*
214 * Disable coherency if this cluster is to be
215 * turned off
216 */
Dan Handley1c54d972014-06-20 12:02:01 +0100217 if (get_plat_config()->flags & CONFIG_HAS_CCI)
Dan Handleybe234f92014-08-04 16:11:15 +0100218 cci_disable_cluster_coherency(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100219
220 /*
221 * Program the power controller to turn the
222 * cluster off
223 */
224 fvp_pwrc_write_pcoffr(mpidr);
225
226 }
227 break;
228
229 case MPIDR_AFFLVL0:
230 if (state == PSCI_STATE_OFF) {
231 /*
232 * Take this cpu out of intra-cluster coherency if
233 * the FVP flavour supports the SMP bit.
234 */
Dan Handley1c54d972014-06-20 12:02:01 +0100235 if (get_plat_config()->flags & CONFIG_CPUECTLR_SMP_BIT) {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236 ectlr = read_cpuectlr();
237 ectlr &= ~CPUECTLR_SMP_BIT;
238 write_cpuectlr(ectlr);
239 }
240
241 /* Program the jump address for the target cpu */
242 linear_id = platform_get_core_pos(mpidr);
Juan Castillo48e84b32014-08-12 13:51:51 +0100243 fvp_mboxes = (mailbox_t *)MBOX_BASE;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100244 fvp_mboxes[linear_id].value = sec_entrypoint;
245 flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
246 sizeof(unsigned long));
247
248 /*
249 * Prevent interrupts from spuriously waking up
250 * this cpu
251 */
Dan Handleyfb42b122014-06-20 09:43:15 +0100252 arm_gic_cpuif_deactivate();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100253
254 /*
255 * Program the power controller to power this
256 * cpu off and enable wakeup interrupts.
257 */
Achin Guptab127cdb2013-11-12 16:40:00 +0000258 fvp_pwrc_set_wen(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100259 fvp_pwrc_write_ppoffr(mpidr);
260 }
261 break;
262
263 default:
264 assert(0);
265 }
266
Achin Gupta4f6ad662013-10-25 09:08:21 +0100267 return rc;
268}
269
270/*******************************************************************************
271 * FVP handler called when an affinity instance has just been powered on after
272 * being turned off earlier. The level and mpidr determine the affinity
273 * instance. The 'state' arg. allows the platform to decide whether the cluster
274 * was turned off prior to wakeup and do what's necessary to setup it up
275 * correctly.
276 ******************************************************************************/
277int fvp_affinst_on_finish(unsigned long mpidr,
278 unsigned int afflvl,
279 unsigned int state)
280{
281 int rc = PSCI_E_SUCCESS;
Dan Handley1c54d972014-06-20 12:02:01 +0100282 unsigned long linear_id;
Dan Handleye2712bc2014-04-10 15:37:22 +0100283 mailbox_t *fvp_mboxes;
Dan Handleyfb42b122014-06-20 09:43:15 +0100284 unsigned int ectlr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100285
286 switch (afflvl) {
287
288 case MPIDR_AFFLVL1:
289 /* Enable coherency if this cluster was off */
Harry Liebel30affd52013-10-30 17:41:48 +0000290 if (state == PSCI_STATE_OFF) {
Achin Guptab2187ab2014-01-17 16:52:29 +0000291
292 /*
293 * This CPU might have woken up whilst the
294 * cluster was attempting to power down. In
295 * this case the FVP power controller will
296 * have a pending cluster power off request
297 * which needs to be cleared by writing to the
298 * PPONR register. This prevents the power
299 * controller from interpreting a subsequent
300 * entry of this cpu into a simple wfi as a
301 * power down request.
302 */
303 fvp_pwrc_write_pponr(mpidr);
304
Dan Handleybe234f92014-08-04 16:11:15 +0100305 fvp_cci_enable();
Harry Liebel30affd52013-10-30 17:41:48 +0000306 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100307 break;
308
309 case MPIDR_AFFLVL0:
310 /*
311 * Ignore the state passed for a cpu. It could only have
312 * been off if we are here.
313 */
314
315 /*
316 * Turn on intra-cluster coherency if the FVP flavour supports
317 * it.
318 */
Dan Handley1c54d972014-06-20 12:02:01 +0100319 if (get_plat_config()->flags & CONFIG_CPUECTLR_SMP_BIT) {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100320 ectlr = read_cpuectlr();
321 ectlr |= CPUECTLR_SMP_BIT;
322 write_cpuectlr(ectlr);
323 }
324
Achin Guptab127cdb2013-11-12 16:40:00 +0000325 /*
326 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
327 * with a cpu power down unless the bit is set again
328 */
329 fvp_pwrc_clr_wen(mpidr);
330
Achin Gupta4f6ad662013-10-25 09:08:21 +0100331 /* Zero the jump address in the mailbox for this cpu */
Juan Castillo48e84b32014-08-12 13:51:51 +0100332 fvp_mboxes = (mailbox_t *)MBOX_BASE;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100333 linear_id = platform_get_core_pos(mpidr);
334 fvp_mboxes[linear_id].value = 0;
335 flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
336 sizeof(unsigned long));
337
Achin Gupta4f6ad662013-10-25 09:08:21 +0100338 /* Enable the gic cpu interface */
Dan Handleyfb42b122014-06-20 09:43:15 +0100339 arm_gic_cpuif_setup();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100340
341 /* TODO: This setup is needed only after a cold boot */
Dan Handleyfb42b122014-06-20 09:43:15 +0100342 arm_gic_pcpu_distif_setup();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100343
Achin Gupta4f6ad662013-10-25 09:08:21 +0100344 break;
345
346 default:
347 assert(0);
348 }
349
350 return rc;
351}
352
353/*******************************************************************************
354 * FVP handler called when an affinity instance has just been powered on after
355 * having been suspended earlier. The level and mpidr determine the affinity
356 * instance.
357 * TODO: At the moment we reuse the on finisher and reinitialize the secure
358 * context. Need to implement a separate suspend finisher.
359 ******************************************************************************/
360int fvp_affinst_suspend_finish(unsigned long mpidr,
361 unsigned int afflvl,
362 unsigned int state)
363{
364 return fvp_affinst_on_finish(mpidr, afflvl, state);
365}
366
367
368/*******************************************************************************
369 * Export the platform handlers to enable psci to invoke them
370 ******************************************************************************/
Dan Handleya4cb68e2014-04-23 13:47:06 +0100371static const plat_pm_ops_t fvp_plat_pm_ops = {
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000372 fvp_affinst_standby,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100373 fvp_affinst_on,
374 fvp_affinst_off,
375 fvp_affinst_suspend,
376 fvp_affinst_on_finish,
377 fvp_affinst_suspend_finish,
378};
379
380/*******************************************************************************
381 * Export the platform specific power ops & initialize the fvp power controller
382 ******************************************************************************/
Dan Handleya4cb68e2014-04-23 13:47:06 +0100383int platform_setup_pm(const plat_pm_ops_t **plat_ops)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100384{
385 *plat_ops = &fvp_plat_pm_ops;
386 return 0;
387}