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Antonio Nino Diazf1b84f62018-07-03 11:58:49 +01001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz9d596c42018-07-12 15:43:07 +01007#include <assert.h>
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +01008#include <debug.h>
9#include <platform_def.h>
10#include <xlat_tables_defs.h>
11#include <xlat_tables_v2.h>
12
13#include "xlat_tables_private.h"
14
15/*
Antonio Nino Diaz67f799e2018-07-15 16:42:01 +010016 * MMU configuration register values for the active translation context. Used
17 * from the MMU assembly helpers.
18 */
19uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
20
21/*
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010022 * Each platform can define the size of its physical and virtual address spaces.
23 * If the platform hasn't defined one or both of them, default to
24 * ADDR_SPACE_SIZE. The latter is deprecated, though.
25 */
26#if ERROR_DEPRECATED
27# ifdef ADDR_SPACE_SIZE
28# error "ADDR_SPACE_SIZE is deprecated. Use PLAT_xxx_ADDR_SPACE_SIZE instead."
29# endif
30#elif defined(ADDR_SPACE_SIZE)
31# ifndef PLAT_PHY_ADDR_SPACE_SIZE
32# define PLAT_PHY_ADDR_SPACE_SIZE ADDR_SPACE_SIZE
33# endif
34# ifndef PLAT_VIRT_ADDR_SPACE_SIZE
35# define PLAT_VIRT_ADDR_SPACE_SIZE ADDR_SPACE_SIZE
36# endif
37#endif
38
39/*
40 * Allocate and initialise the default translation context for the BL image
41 * currently executing.
42 */
43REGISTER_XLAT_CONTEXT(tf, MAX_MMAP_REGIONS, MAX_XLAT_TABLES,
44 PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE);
45
46void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, size_t size,
47 unsigned int attr)
48{
49 mmap_region_t mm = MAP_REGION(base_pa, base_va, size, attr);
50
51 mmap_add_region_ctx(&tf_xlat_ctx, &mm);
52}
53
54void mmap_add(const mmap_region_t *mm)
55{
56 mmap_add_ctx(&tf_xlat_ctx, mm);
57}
58
59#if PLAT_XLAT_TABLES_DYNAMIC
60
61int mmap_add_dynamic_region(unsigned long long base_pa, uintptr_t base_va,
62 size_t size, unsigned int attr)
63{
64 mmap_region_t mm = MAP_REGION(base_pa, base_va, size, attr);
65
66 return mmap_add_dynamic_region_ctx(&tf_xlat_ctx, &mm);
67}
68
69int mmap_remove_dynamic_region(uintptr_t base_va, size_t size)
70{
71 return mmap_remove_dynamic_region_ctx(&tf_xlat_ctx,
72 base_va, size);
73}
74
75#endif /* PLAT_XLAT_TABLES_DYNAMIC */
76
77void init_xlat_tables(void)
78{
Antonio Nino Diaz9d596c42018-07-12 15:43:07 +010079 assert(tf_xlat_ctx.xlat_regime == EL_REGIME_INVALID);
80
81 int current_el = xlat_arch_current_el();
82
83 if (current_el == 1) {
84 tf_xlat_ctx.xlat_regime = EL1_EL0_REGIME;
85 } else {
86 assert(current_el == 3);
87 tf_xlat_ctx.xlat_regime = EL3_REGIME;
88 }
89
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010090 init_xlat_tables_ctx(&tf_xlat_ctx);
91}
92
93/*
94 * If dynamic allocation of new regions is disabled then by the time we call the
95 * function enabling the MMU, we'll have registered all the memory regions to
96 * map for the system's lifetime. Therefore, at this point we know the maximum
97 * physical address that will ever be mapped.
98 *
99 * If dynamic allocation is enabled then we can't make any such assumption
100 * because the maximum physical address could get pushed while adding a new
101 * region. Therefore, in this case we have to assume that the whole address
102 * space size might be mapped.
103 */
104#ifdef PLAT_XLAT_TABLES_DYNAMIC
105#define MAX_PHYS_ADDR tf_xlat_ctx.pa_max_address
106#else
107#define MAX_PHYS_ADDR tf_xlat_ctx.max_pa
108#endif
109
110#ifdef AARCH32
111
112void enable_mmu_secure(unsigned int flags)
113{
Antonio Nino Diaz67f799e2018-07-15 16:42:01 +0100114 setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
115 tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
Antonio Nino Diaz9d596c42018-07-12 15:43:07 +0100116 tf_xlat_ctx.va_max_address, EL1_EL0_REGIME);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100117 enable_mmu_direct(flags);
118}
119
120#else
121
122void enable_mmu_el1(unsigned int flags)
123{
Antonio Nino Diaz67f799e2018-07-15 16:42:01 +0100124 setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
125 tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
Antonio Nino Diaz9d596c42018-07-12 15:43:07 +0100126 tf_xlat_ctx.va_max_address, EL1_EL0_REGIME);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100127 enable_mmu_direct_el1(flags);
128}
129
130void enable_mmu_el3(unsigned int flags)
131{
Antonio Nino Diaz67f799e2018-07-15 16:42:01 +0100132 setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
133 tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
Antonio Nino Diaz9d596c42018-07-12 15:43:07 +0100134 tf_xlat_ctx.va_max_address, EL3_REGIME);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100135 enable_mmu_direct_el3(flags);
136}
137
138#endif /* AARCH32 */