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Haojian Zhuang5f281b32017-05-24 08:45:05 +08001/*
Deepika Bhavnani36e296f2019-12-13 10:49:20 -06002 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang5f281b32017-05-24 08:45:05 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Haojian Zhuang5f281b32017-05-24 08:45:05 +08009
10#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/tbbr/tbbr_img_def.h>
12#include <lib/utils_def.h>
13#include <plat/common/common_def.h>
14
Michael Brandlafdff3c2018-02-22 16:30:30 +010015#include <hikey_def.h>
16#include <hikey_layout.h> /* BL memory region sizes, etc */
Haojian Zhuang5f281b32017-05-24 08:45:05 +080017
Victor Chong2d9a42d2017-08-17 15:21:10 +090018/* Special value used to verify platform parameters from BL2 to BL3-1 */
19#define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
20
Haojian Zhuang5f281b32017-05-24 08:45:05 +080021/*
Haojian Zhuang5f281b32017-05-24 08:45:05 +080022 * Generic platform constants
23 */
24
25/* Size of cacheable stacks */
Teddy Reed349cf892018-06-22 22:23:36 -040026#define PLATFORM_STACK_SIZE 0x1000
Haojian Zhuang5f281b32017-05-24 08:45:05 +080027
28#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
29
30#define PLATFORM_CACHE_LINE_SIZE 64
Deepika Bhavnani36e296f2019-12-13 10:49:20 -060031#define PLATFORM_CLUSTER_COUNT U(2)
32#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4)
Haojian Zhuang5f281b32017-05-24 08:45:05 +080033#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
34 PLATFORM_CORE_COUNT_PER_CLUSTER)
Michael Brandlafdff3c2018-02-22 16:30:30 +010035#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2)
Haojian Zhuang5f281b32017-05-24 08:45:05 +080036#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
Deepika Bhavnani36e296f2019-12-13 10:49:20 -060037 PLATFORM_CLUSTER_COUNT + U(1))
Haojian Zhuang5f281b32017-05-24 08:45:05 +080038
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010039#define PLAT_MAX_RET_STATE U(1)
40#define PLAT_MAX_OFF_STATE U(2)
Haojian Zhuang5f281b32017-05-24 08:45:05 +080041
42#define MAX_IO_DEVICES 3
43#define MAX_IO_HANDLES 4
44/* eMMC RPMB and eMMC User Data */
Yann Gautier37966212018-12-03 13:38:06 +010045#define MAX_IO_BLOCK_DEVICES U(2)
Haojian Zhuang5f281b32017-05-24 08:45:05 +080046
47/* GIC related constants (no GICR in GIC-400) */
48#define PLAT_ARM_GICD_BASE 0xF6801000
49#define PLAT_ARM_GICC_BASE 0xF6802000
50#define PLAT_ARM_GICH_BASE 0xF6804000
51#define PLAT_ARM_GICV_BASE 0xF6806000
52
Haojian Zhuang5f281b32017-05-24 08:45:05 +080053/*
54 * Platform specific page table and MMU setup constants
55 */
Antonio Nino Diaz42c7bbd2018-09-24 17:15:05 +010056#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
57#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
Haojian Zhuang5f281b32017-05-24 08:45:05 +080058
Roberto Vargas82477962017-10-23 08:22:17 +010059#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
Haojian Zhuang5f281b32017-05-24 08:45:05 +080060#define MAX_XLAT_TABLES 3
61#endif
62
Roberto Vargas82477962017-10-23 08:22:17 +010063#ifdef IMAGE_BL31
Victor Chongb9a8db22017-05-28 00:14:25 +090064#define MAX_XLAT_TABLES 4
Victor Chong7d787f52017-08-16 13:53:56 +090065#endif
66
Roberto Vargas82477962017-10-23 08:22:17 +010067#ifdef IMAGE_BL2
Victor Chong7d787f52017-08-16 13:53:56 +090068#define MAX_XLAT_TABLES 4
Victor Chongb9a8db22017-05-28 00:14:25 +090069#endif
70
Haojian Zhuang5f281b32017-05-24 08:45:05 +080071#define MAX_MMAP_REGIONS 16
72
Haojian Zhuang5f281b32017-05-24 08:45:05 +080073/*
74 * Declarations and constants to access the mailboxes safely. Each mailbox is
75 * aligned on the biggest cache line size in the platform. This is known only
76 * to the platform as it might have a combination of integrated and external
77 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
78 * line at any cache level. They could belong to different cpus/clusters &
79 * get written while being protected by different locks causing corruption of
80 * a valid mailbox address.
81 */
82#define CACHE_WRITEBACK_SHIFT 6
83#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
84
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010085#endif /* PLATFORM_DEF_H */