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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Jon Medhurstd0212c22014-02-11 14:48:56 +000031#include <assert.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <gic.h>
33#include <mmio.h>
34
35/*******************************************************************************
Sandrine Bailleux27866d82013-10-25 15:33:39 +010036 * GIC Distributor interface accessors for reading entire registers
Achin Gupta4f6ad662013-10-25 09:08:21 +010037 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +010038
39unsigned int gicd_read_igroupr(unsigned int base, unsigned int id)
40{
41 unsigned n = id >> IGROUPR_SHIFT;
42 return mmio_read_32(base + GICD_IGROUPR + (n << 2));
43}
44
45unsigned int gicd_read_isenabler(unsigned int base, unsigned int id)
46{
47 unsigned n = id >> ISENABLER_SHIFT;
48 return mmio_read_32(base + GICD_ISENABLER + (n << 2));
49}
50
51unsigned int gicd_read_icenabler(unsigned int base, unsigned int id)
52{
53 unsigned n = id >> ICENABLER_SHIFT;
54 return mmio_read_32(base + GICD_ICENABLER + (n << 2));
55}
56
57unsigned int gicd_read_ispendr(unsigned int base, unsigned int id)
58{
59 unsigned n = id >> ISPENDR_SHIFT;
60 return mmio_read_32(base + GICD_ISPENDR + (n << 2));
61}
62
63unsigned int gicd_read_icpendr(unsigned int base, unsigned int id)
64{
65 unsigned n = id >> ICPENDR_SHIFT;
66 return mmio_read_32(base + GICD_ICPENDR + (n << 2));
67}
68
69unsigned int gicd_read_isactiver(unsigned int base, unsigned int id)
70{
71 unsigned n = id >> ISACTIVER_SHIFT;
72 return mmio_read_32(base + GICD_ISACTIVER + (n << 2));
73}
74
75unsigned int gicd_read_icactiver(unsigned int base, unsigned int id)
76{
77 unsigned n = id >> ICACTIVER_SHIFT;
78 return mmio_read_32(base + GICD_ICACTIVER + (n << 2));
79}
80
81unsigned int gicd_read_ipriorityr(unsigned int base, unsigned int id)
82{
83 unsigned n = id >> IPRIORITYR_SHIFT;
84 return mmio_read_32(base + GICD_IPRIORITYR + (n << 2));
85}
86
87unsigned int gicd_read_itargetsr(unsigned int base, unsigned int id)
88{
89 unsigned n = id >> ITARGETSR_SHIFT;
90 return mmio_read_32(base + GICD_ITARGETSR + (n << 2));
91}
92
93unsigned int gicd_read_icfgr(unsigned int base, unsigned int id)
94{
95 unsigned n = id >> ICFGR_SHIFT;
96 return mmio_read_32(base + GICD_ICFGR + (n << 2));
97}
98
Achin Gupta4f6ad662013-10-25 09:08:21 +010099unsigned int gicd_read_cpendsgir(unsigned int base, unsigned int id)
100{
101 unsigned n = id >> CPENDSGIR_SHIFT;
102 return mmio_read_32(base + GICD_CPENDSGIR + (n << 2));
103}
104
105unsigned int gicd_read_spendsgir(unsigned int base, unsigned int id)
106{
107 unsigned n = id >> SPENDSGIR_SHIFT;
108 return mmio_read_32(base + GICD_SPENDSGIR + (n << 2));
109}
110
111/*******************************************************************************
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100112 * GIC Distributor interface accessors for writing entire registers
Achin Gupta4f6ad662013-10-25 09:08:21 +0100113 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +0100114
115void gicd_write_igroupr(unsigned int base, unsigned int id, unsigned int val)
116{
117 unsigned n = id >> IGROUPR_SHIFT;
118 mmio_write_32(base + GICD_IGROUPR + (n << 2), val);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100119}
120
121void gicd_write_isenabler(unsigned int base, unsigned int id, unsigned int val)
122{
123 unsigned n = id >> ISENABLER_SHIFT;
124 mmio_write_32(base + GICD_ISENABLER + (n << 2), val);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100125}
126
127void gicd_write_icenabler(unsigned int base, unsigned int id, unsigned int val)
128{
129 unsigned n = id >> ICENABLER_SHIFT;
130 mmio_write_32(base + GICD_ICENABLER + (n << 2), val);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100131}
132
133void gicd_write_ispendr(unsigned int base, unsigned int id, unsigned int val)
134{
135 unsigned n = id >> ISPENDR_SHIFT;
136 mmio_write_32(base + GICD_ISPENDR + (n << 2), val);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137}
138
139void gicd_write_icpendr(unsigned int base, unsigned int id, unsigned int val)
140{
141 unsigned n = id >> ICPENDR_SHIFT;
142 mmio_write_32(base + GICD_ICPENDR + (n << 2), val);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100143}
144
145void gicd_write_isactiver(unsigned int base, unsigned int id, unsigned int val)
146{
147 unsigned n = id >> ISACTIVER_SHIFT;
148 mmio_write_32(base + GICD_ISACTIVER + (n << 2), val);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100149}
150
151void gicd_write_icactiver(unsigned int base, unsigned int id, unsigned int val)
152{
153 unsigned n = id >> ICACTIVER_SHIFT;
154 mmio_write_32(base + GICD_ICACTIVER + (n << 2), val);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100155}
156
157void gicd_write_ipriorityr(unsigned int base, unsigned int id, unsigned int val)
158{
159 unsigned n = id >> IPRIORITYR_SHIFT;
160 mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100161}
162
163void gicd_write_itargetsr(unsigned int base, unsigned int id, unsigned int val)
164{
165 unsigned n = id >> ITARGETSR_SHIFT;
166 mmio_write_32(base + GICD_ITARGETSR + (n << 2), val);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100167}
168
169void gicd_write_icfgr(unsigned int base, unsigned int id, unsigned int val)
170{
171 unsigned n = id >> ICFGR_SHIFT;
172 mmio_write_32(base + GICD_ICFGR + (n << 2), val);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100173}
174
175void gicd_write_cpendsgir(unsigned int base, unsigned int id, unsigned int val)
176{
177 unsigned n = id >> CPENDSGIR_SHIFT;
178 mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100179}
180
181void gicd_write_spendsgir(unsigned int base, unsigned int id, unsigned int val)
182{
183 unsigned n = id >> SPENDSGIR_SHIFT;
184 mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100185}
186
187/*******************************************************************************
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100188 * GIC Distributor interface accessors for individual interrupt manipulation
Achin Gupta4f6ad662013-10-25 09:08:21 +0100189 ******************************************************************************/
190unsigned int gicd_get_igroupr(unsigned int base, unsigned int id)
191{
192 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
193 unsigned int reg_val = gicd_read_igroupr(base, id);
194
195 return (reg_val >> bit_num) & 0x1;
196}
197
198void gicd_set_igroupr(unsigned int base, unsigned int id)
199{
200 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
201 unsigned int reg_val = gicd_read_igroupr(base, id);
202
203 gicd_write_igroupr(base, id, reg_val | (1 << bit_num));
Achin Gupta4f6ad662013-10-25 09:08:21 +0100204}
205
206void gicd_clr_igroupr(unsigned int base, unsigned int id)
207{
208 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
209 unsigned int reg_val = gicd_read_igroupr(base, id);
210
211 gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num));
Achin Gupta4f6ad662013-10-25 09:08:21 +0100212}
213
214void gicd_set_isenabler(unsigned int base, unsigned int id)
215{
216 unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1);
217 unsigned int reg_val = gicd_read_isenabler(base, id);
218
219 gicd_write_isenabler(base, id, reg_val | (1 << bit_num));
Achin Gupta4f6ad662013-10-25 09:08:21 +0100220}
221
222void gicd_set_icenabler(unsigned int base, unsigned int id)
223{
224 unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1);
225 unsigned int reg_val = gicd_read_icenabler(base, id);
226
227 gicd_write_icenabler(base, id, reg_val & ~(1 << bit_num));
Achin Gupta4f6ad662013-10-25 09:08:21 +0100228}
229
230void gicd_set_ispendr(unsigned int base, unsigned int id)
231{
232 unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1);
233 unsigned int reg_val = gicd_read_ispendr(base, id);
234
235 gicd_write_ispendr(base, id, reg_val | (1 << bit_num));
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236}
237
238void gicd_set_icpendr(unsigned int base, unsigned int id)
239{
240 unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1);
241 unsigned int reg_val = gicd_read_icpendr(base, id);
242
243 gicd_write_icpendr(base, id, reg_val & ~(1 << bit_num));
Achin Gupta4f6ad662013-10-25 09:08:21 +0100244}
245
246void gicd_set_isactiver(unsigned int base, unsigned int id)
247{
248 unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
249 unsigned int reg_val = gicd_read_isactiver(base, id);
250
251 gicd_write_isactiver(base, id, reg_val | (1 << bit_num));
Achin Gupta4f6ad662013-10-25 09:08:21 +0100252}
253
254void gicd_set_icactiver(unsigned int base, unsigned int id)
255{
256 unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1);
257 unsigned int reg_val = gicd_read_icactiver(base, id);
258
259 gicd_write_icactiver(base, id, reg_val & ~(1 << bit_num));
Achin Gupta4f6ad662013-10-25 09:08:21 +0100260}
261
262/*
263 * Make sure that the interrupt's group is set before expecting
264 * this function to do its job correctly.
265 */
266void gicd_set_ipriorityr(unsigned int base, unsigned int id, unsigned int pri)
267{
Jon Medhurstd0212c22014-02-11 14:48:56 +0000268 unsigned int reg = base + GICD_IPRIORITYR + (id & ~3);
269 unsigned int shift = (id & 3) << 3;
270 unsigned int reg_val = mmio_read_32(reg);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100271
272 /*
273 * Enforce ARM recommendation to manage priority values such
274 * that group1 interrupts always have a lower priority than
Jon Medhurstd0212c22014-02-11 14:48:56 +0000275 * group0 interrupts.
276 * Note, lower numerical values are higher priorities so the comparison
277 * checks below are reversed from what might be expected.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100278 */
Jon Medhurstd0212c22014-02-11 14:48:56 +0000279 assert(gicd_get_igroupr(base, id) == GRP1 ?
280 pri >= GIC_HIGHEST_NS_PRIORITY &&
281 pri <= GIC_LOWEST_NS_PRIORITY :
282 pri >= GIC_HIGHEST_SEC_PRIORITY &&
283 pri <= GIC_LOWEST_SEC_PRIORITY);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100284
Jon Medhurstd0212c22014-02-11 14:48:56 +0000285 reg_val &= ~(GIC_PRI_MASK << shift);
286 reg_val |= (pri & GIC_PRI_MASK) << shift;
287 mmio_write_32(reg, reg_val);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100288}
289
290void gicd_set_itargetsr(unsigned int base, unsigned int id, unsigned int iface)
291{
292 unsigned byte_off = id & ((1 << ITARGETSR_SHIFT) - 1);
293 unsigned int reg_val = gicd_read_itargetsr(base, id);
294
295 gicd_write_itargetsr(base, id, reg_val |
296 (1 << iface) << (byte_off << 3));
Achin Gupta4f6ad662013-10-25 09:08:21 +0100297}
298