blob: 009f08acfd7f803b9487ae22231237c4c68955a8 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32
33 .weak cpu_reset_handler
34
35
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000036 .section .text, "ax"; .align 3
Achin Gupta4f6ad662013-10-25 09:08:21 +010037
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +000038cpu_reset_handler: ; .type cpu_reset_handler, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +010039 mov x19, x30 // lr
40
41 /* ---------------------------------------------
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000042 * As a bare minimal enable the SMP bit.
Achin Gupta4f6ad662013-10-25 09:08:21 +010043 * ---------------------------------------------
44 */
Achin Gupta4f6ad662013-10-25 09:08:21 +010045 bl read_midr
46 lsr x0, x0, #MIDR_PN_SHIFT
47 and x0, x0, #MIDR_PN_MASK
48 cmp x0, #MIDR_PN_A57
49 b.eq smp_setup_begin
50 cmp x0, #MIDR_PN_A53
51 b.ne smp_setup_end
52smp_setup_begin:
53 bl read_cpuectlr
54 orr x0, x0, #CPUECTLR_SMP_BIT
55 bl write_cpuectlr
56smp_setup_end:
Achin Gupta4f6ad662013-10-25 09:08:21 +010057 ret x19