Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / cf45aee12d86299f20f63d4921a341201b58a281 / . / plat / nvidia / tegra / soc / t186 / platform_t186.mk
blob: a11a77bf59cb90f765d878d7cd07a6b980486b59 [file] [log] [blame]
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]1#
Varun Wadekarbe57abb2019-01-03 10:44:22 -0800[diff] [blame]2# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekarbf601c22018-06-12 16:55:06 -0700[diff] [blame]3# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]4#
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]5# SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]6#
7
8# platform configs
Varun Wadekara0f26972016-03-11 17:18:51 -0800[diff] [blame]9ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 1
10$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
11
Varun Wadekarad2824f2016-03-28 13:44:35 -0700[diff] [blame]12ENABLE_CHIP_VERIFICATION_HARNESS := 0
13$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS))
14
Varun Wadekar94701ff2016-05-23 11:47:34 -0700[diff] [blame]15RESET_TO_BL31 := 1
16
17PROGRAMMABLE_RESET_ADDRESS := 1
18
19COLD_BOOT_SINGLE_CPU := 1
20
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]21# platform settings
Varun Wadekar94d85322015-11-30 12:05:04 -0800[diff] [blame]22TZDRAM_BASE := 0x30000000
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]23$(eval $(call add_define,TZDRAM_BASE))
24
25PLATFORM_CLUSTER_COUNT := 2
26$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
27
28PLATFORM_MAX_CPUS_PER_CLUSTER := 4
29$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
30
Varun Wadekard64db962016-09-23 14:28:16 -0700[diff] [blame]31MAX_XLAT_TABLES := 24
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]32$(eval $(call add_define,MAX_XLAT_TABLES))
33
Varun Wadekarbe57abb2019-01-03 10:44:22 -0800[diff] [blame]34MAX_MMAP_REGIONS := 25
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]35$(eval $(call add_define,MAX_MMAP_REGIONS))
36
37# platform files
38PLAT_INCLUDES += -I${SOC_DIR}/drivers/include
39
Varun Wadekar50a33032017-11-15 15:46:38 -0800[diff] [blame]40BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
41 lib/cpus/aarch64/denver.S \
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]42 lib/cpus/aarch64/cortex_a57.S \
Varun Wadekaree25e822017-06-28 14:38:19 -0700[diff] [blame]43 ${COMMON_DIR}/drivers/gpcdma/gpcdma.c \
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]44 ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
Varun Wadekarbd2b4142016-12-12 16:46:44 -0800[diff] [blame]45 ${COMMON_DIR}/drivers/smmu/smmu.c \
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]46 ${SOC_DIR}/drivers/mce/mce.c \
47 ${SOC_DIR}/drivers/mce/ari.c \
48 ${SOC_DIR}/drivers/mce/nvg.c \
49 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530[diff] [blame]50 ${SOC_DIR}/plat_memctrl.c \
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]51 ${SOC_DIR}/plat_psci_handlers.c \
52 ${SOC_DIR}/plat_setup.c \
53 ${SOC_DIR}/plat_secondary.c \
Varun Wadekar93bed2a2016-03-18 13:07:33 -0700[diff] [blame]54 ${SOC_DIR}/plat_sip_calls.c \
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]55 ${SOC_DIR}/plat_smmu.c \
Varun Wadekar93bed2a2016-03-18 13:07:33 -0700[diff] [blame]56 ${SOC_DIR}/plat_trampoline.S
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530[diff] [blame]57
Varun Wadekarb01d3bb2017-07-25 13:29:52 -0700[diff] [blame]58# Enable workarounds for selected Cortex-A57 erratas.
59A57_DISABLE_NON_TEMPORAL_HINT := 1
60ERRATA_A57_806969 := 1
61ERRATA_A57_813419 := 1
62ERRATA_A57_813420 := 1
63ERRATA_A57_826974 := 1
64ERRATA_A57_826977 := 1
65ERRATA_A57_828024 := 1
66ERRATA_A57_829520 := 1
67ERRATA_A57_833471 := 1
Varun Wadekarbf601c22018-06-12 16:55:06 -0700[diff] [blame]68
69# Enable higher performance Non-cacheable load forwarding
70A57_ENABLE_NONCACHEABLE_LOAD_FWD := 1