Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 1 | /* |
Javier Almansa Sobrino | 8c8107e | 2023-05-03 12:16:11 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 7 | #include <assert.h> |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 8 | #include <stdbool.h> |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 9 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | |
| 11 | #include <arch.h> |
Antonio Nino Diaz | c326c34 | 2019-01-11 11:20:10 +0000 | [diff] [blame] | 12 | #include <arch_features.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 13 | #include <arch_helpers.h> |
| 14 | #include <lib/cassert.h> |
| 15 | #include <lib/utils_def.h> |
| 16 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 17 | |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 18 | #include "../xlat_tables_private.h" |
| 19 | |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 20 | /* |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 21 | * Returns true if the provided granule size is supported, false otherwise. |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 22 | */ |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 23 | bool xlat_arch_is_granule_size_supported(size_t size) |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 24 | { |
Javier Almansa Sobrino | 8c8107e | 2023-05-03 12:16:11 +0100 | [diff] [blame] | 25 | unsigned int tgranx; |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 26 | |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 27 | if (size == PAGE_SIZE_4KB) { |
Javier Almansa Sobrino | 8c8107e | 2023-05-03 12:16:11 +0100 | [diff] [blame] | 28 | tgranx = read_id_aa64mmfr0_el0_tgran4_field(); |
| 29 | /* MSB of TGRAN4 field will be '1' for unsupported feature */ |
| 30 | return ((tgranx >= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED) && |
| 31 | (tgranx < 8U)); |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 32 | } else if (size == PAGE_SIZE_16KB) { |
Javier Almansa Sobrino | 8c8107e | 2023-05-03 12:16:11 +0100 | [diff] [blame] | 33 | tgranx = read_id_aa64mmfr0_el0_tgran16_field(); |
| 34 | return (tgranx >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED); |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 35 | } else if (size == PAGE_SIZE_64KB) { |
Javier Almansa Sobrino | 8c8107e | 2023-05-03 12:16:11 +0100 | [diff] [blame] | 36 | tgranx = read_id_aa64mmfr0_el0_tgran64_field(); |
| 37 | /* MSB of TGRAN64 field will be '1' for unsupported feature */ |
| 38 | return ((tgranx >= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED) && |
| 39 | (tgranx < 8U)); |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 40 | } else { |
Javier Almansa Sobrino | 8c8107e | 2023-05-03 12:16:11 +0100 | [diff] [blame] | 41 | return false; |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 42 | } |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 43 | } |
| 44 | |
| 45 | size_t xlat_arch_get_max_supported_granule_size(void) |
| 46 | { |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 47 | if (xlat_arch_is_granule_size_supported(PAGE_SIZE_64KB)) { |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 48 | return PAGE_SIZE_64KB; |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 49 | } else if (xlat_arch_is_granule_size_supported(PAGE_SIZE_16KB)) { |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 50 | return PAGE_SIZE_16KB; |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 51 | } else { |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 52 | assert(xlat_arch_is_granule_size_supported(PAGE_SIZE_4KB)); |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 53 | return PAGE_SIZE_4KB; |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 54 | } |
| 55 | } |
| 56 | |
Zelalem Aweke | 173c6a2 | 2021-07-08 17:23:04 -0500 | [diff] [blame] | 57 | /* |
| 58 | * Determine the physical address space encoded in the 'attr' parameter. |
| 59 | * |
| 60 | * The physical address will fall into one of four spaces; secure, |
| 61 | * nonsecure, root, or realm if RME is enabled, or one of two spaces; |
| 62 | * secure and nonsecure otherwise. |
| 63 | */ |
| 64 | uint32_t xlat_arch_get_pas(uint32_t attr) |
| 65 | { |
| 66 | uint32_t pas = MT_PAS(attr); |
| 67 | |
| 68 | switch (pas) { |
| 69 | #if ENABLE_RME |
| 70 | /* TTD.NSE = 1 and TTD.NS = 1 for Realm PAS */ |
| 71 | case MT_REALM: |
| 72 | return LOWER_ATTRS(EL3_S1_NSE | NS); |
| 73 | /* TTD.NSE = 1 and TTD.NS = 0 for Root PAS */ |
| 74 | case MT_ROOT: |
| 75 | return LOWER_ATTRS(EL3_S1_NSE); |
| 76 | #endif |
| 77 | case MT_NS: |
| 78 | return LOWER_ATTRS(NS); |
| 79 | default: /* MT_SECURE */ |
| 80 | return 0U; |
| 81 | } |
| 82 | } |
| 83 | |
Antonio Nino Diaz | bafc753 | 2017-10-25 11:53:25 +0100 | [diff] [blame] | 84 | unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 85 | { |
| 86 | /* Physical address can't exceed 48 bits */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 87 | assert((max_addr & ADDR_MASK_48_TO_63) == 0U); |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 88 | |
| 89 | /* 48 bits address */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 90 | if ((max_addr & ADDR_MASK_44_TO_47) != 0U) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 91 | return TCR_PS_BITS_256TB; |
| 92 | |
| 93 | /* 44 bits address */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 94 | if ((max_addr & ADDR_MASK_42_TO_43) != 0U) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 95 | return TCR_PS_BITS_16TB; |
| 96 | |
| 97 | /* 42 bits address */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 98 | if ((max_addr & ADDR_MASK_40_TO_41) != 0U) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 99 | return TCR_PS_BITS_4TB; |
| 100 | |
| 101 | /* 40 bits address */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 102 | if ((max_addr & ADDR_MASK_36_TO_39) != 0U) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 103 | return TCR_PS_BITS_1TB; |
| 104 | |
| 105 | /* 36 bits address */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 106 | if ((max_addr & ADDR_MASK_32_TO_35) != 0U) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 107 | return TCR_PS_BITS_64GB; |
| 108 | |
| 109 | return TCR_PS_BITS_4GB; |
| 110 | } |
| 111 | |
Antonio Nino Diaz | 3759e3f | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 112 | #if ENABLE_ASSERTIONS |
Antonio Nino Diaz | b9ae5db | 2018-05-02 11:23:56 +0100 | [diff] [blame] | 113 | /* |
| 114 | * Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is |
| 115 | * supported in ARMv8.2 onwards. |
| 116 | */ |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 117 | static const unsigned int pa_range_bits_arr[] = { |
| 118 | PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, |
Antonio Nino Diaz | b9ae5db | 2018-05-02 11:23:56 +0100 | [diff] [blame] | 119 | PARANGE_0101, PARANGE_0110 |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 120 | }; |
| 121 | |
Sandrine Bailleux | c5b6377 | 2017-05-31 13:31:48 +0100 | [diff] [blame] | 122 | unsigned long long xlat_arch_get_max_supported_pa(void) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 123 | { |
| 124 | u_register_t pa_range = read_id_aa64mmfr0_el1() & |
| 125 | ID_AA64MMFR0_EL1_PARANGE_MASK; |
| 126 | |
| 127 | /* All other values are reserved */ |
| 128 | assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); |
| 129 | |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 130 | return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL; |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 131 | } |
Sathees Balya | 7415597 | 2019-01-25 11:36:01 +0000 | [diff] [blame] | 132 | |
| 133 | /* |
| 134 | * Return minimum virtual address space size supported by the architecture |
| 135 | */ |
| 136 | uintptr_t xlat_get_min_virt_addr_space_size(void) |
| 137 | { |
| 138 | uintptr_t ret; |
| 139 | |
| 140 | if (is_armv8_4_ttst_present()) |
| 141 | ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST; |
| 142 | else |
| 143 | ret = MIN_VIRT_ADDR_SPACE_SIZE; |
| 144 | |
| 145 | return ret; |
| 146 | } |
Antonio Nino Diaz | 3759e3f | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 147 | #endif /* ENABLE_ASSERTIONS*/ |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 148 | |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 149 | bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 150 | { |
Antonio Nino Diaz | dcf9d92 | 2017-10-04 16:52:15 +0100 | [diff] [blame] | 151 | if (ctx->xlat_regime == EL1_EL0_REGIME) { |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 152 | assert(xlat_arch_current_el() >= 1U); |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 153 | return (read_sctlr_el1() & SCTLR_M_BIT) != 0U; |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 154 | } else if (ctx->xlat_regime == EL2_REGIME) { |
| 155 | assert(xlat_arch_current_el() >= 2U); |
| 156 | return (read_sctlr_el2() & SCTLR_M_BIT) != 0U; |
Antonio Nino Diaz | dcf9d92 | 2017-10-04 16:52:15 +0100 | [diff] [blame] | 157 | } else { |
| 158 | assert(ctx->xlat_regime == EL3_REGIME); |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 159 | assert(xlat_arch_current_el() >= 3U); |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 160 | return (read_sctlr_el3() & SCTLR_M_BIT) != 0U; |
Antonio Nino Diaz | dcf9d92 | 2017-10-04 16:52:15 +0100 | [diff] [blame] | 161 | } |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 162 | } |
| 163 | |
Antonio Nino Diaz | 37a5efa | 2018-08-07 12:47:12 +0100 | [diff] [blame] | 164 | bool is_dcache_enabled(void) |
| 165 | { |
Masahiro Yamada | 0a3c95b | 2020-04-02 16:20:21 +0900 | [diff] [blame] | 166 | unsigned int el = get_current_el_maybe_constant(); |
Antonio Nino Diaz | 37a5efa | 2018-08-07 12:47:12 +0100 | [diff] [blame] | 167 | |
| 168 | if (el == 1U) { |
| 169 | return (read_sctlr_el1() & SCTLR_C_BIT) != 0U; |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 170 | } else if (el == 2U) { |
| 171 | return (read_sctlr_el2() & SCTLR_C_BIT) != 0U; |
Antonio Nino Diaz | 37a5efa | 2018-08-07 12:47:12 +0100 | [diff] [blame] | 172 | } else { |
| 173 | return (read_sctlr_el3() & SCTLR_C_BIT) != 0U; |
| 174 | } |
| 175 | } |
| 176 | |
Antonio Nino Diaz | 44d3c21 | 2018-07-05 08:11:48 +0100 | [diff] [blame] | 177 | uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime) |
| 178 | { |
| 179 | if (xlat_regime == EL1_EL0_REGIME) { |
| 180 | return UPPER_ATTRS(UXN) | UPPER_ATTRS(PXN); |
| 181 | } else { |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 182 | assert((xlat_regime == EL2_REGIME) || |
| 183 | (xlat_regime == EL3_REGIME)); |
Antonio Nino Diaz | 44d3c21 | 2018-07-05 08:11:48 +0100 | [diff] [blame] | 184 | return UPPER_ATTRS(XN); |
| 185 | } |
| 186 | } |
Antonio Nino Diaz | dcf9d92 | 2017-10-04 16:52:15 +0100 | [diff] [blame] | 187 | |
Antonio Nino Diaz | ad5dc7f | 2018-07-11 09:46:45 +0100 | [diff] [blame] | 188 | void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime) |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 189 | { |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 190 | /* |
| 191 | * Ensure the translation table write has drained into memory before |
| 192 | * invalidating the TLB entry. |
| 193 | */ |
| 194 | dsbishst(); |
| 195 | |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 196 | /* |
| 197 | * This function only supports invalidation of TLB entries for the EL3 |
| 198 | * and EL1&0 translation regimes. |
| 199 | * |
| 200 | * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher |
| 201 | * exception level (see section D4.9.2 of the ARM ARM rev B.a). |
| 202 | */ |
| 203 | if (xlat_regime == EL1_EL0_REGIME) { |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 204 | assert(xlat_arch_current_el() >= 1U); |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 205 | tlbivaae1is(TLBI_ADDR(va)); |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 206 | } else if (xlat_regime == EL2_REGIME) { |
| 207 | assert(xlat_arch_current_el() >= 2U); |
| 208 | tlbivae2is(TLBI_ADDR(va)); |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 209 | } else { |
| 210 | assert(xlat_regime == EL3_REGIME); |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 211 | assert(xlat_arch_current_el() >= 3U); |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 212 | tlbivae3is(TLBI_ADDR(va)); |
| 213 | } |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | void xlat_arch_tlbi_va_sync(void) |
| 217 | { |
| 218 | /* |
| 219 | * A TLB maintenance instruction can complete at any time after |
| 220 | * it is issued, but is only guaranteed to be complete after the |
| 221 | * execution of DSB by the PE that executed the TLB maintenance |
| 222 | * instruction. After the TLB invalidate instruction is |
| 223 | * complete, no new memory accesses using the invalidated TLB |
| 224 | * entries will be observed by any observer of the system |
| 225 | * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph |
| 226 | * "Ordering and completion of TLB maintenance instructions". |
| 227 | */ |
| 228 | dsbish(); |
| 229 | |
| 230 | /* |
| 231 | * The effects of a completed TLB maintenance instruction are |
| 232 | * only guaranteed to be visible on the PE that executed the |
| 233 | * instruction after the execution of an ISB instruction by the |
| 234 | * PE that executed the TLB maintenance instruction. |
| 235 | */ |
| 236 | isb(); |
| 237 | } |
| 238 | |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 239 | unsigned int xlat_arch_current_el(void) |
Antonio Nino Diaz | efabaa9 | 2017-04-27 13:30:22 +0100 | [diff] [blame] | 240 | { |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 241 | unsigned int el = (unsigned int)GET_EL(read_CurrentEl()); |
Antonio Nino Diaz | efabaa9 | 2017-04-27 13:30:22 +0100 | [diff] [blame] | 242 | |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 243 | assert(el > 0U); |
Antonio Nino Diaz | efabaa9 | 2017-04-27 13:30:22 +0100 | [diff] [blame] | 244 | |
| 245 | return el; |
| 246 | } |
| 247 | |
Antonio Nino Diaz | 67f799e | 2018-07-15 16:42:01 +0100 | [diff] [blame] | 248 | void setup_mmu_cfg(uint64_t *params, unsigned int flags, |
| 249 | const uint64_t *base_table, unsigned long long max_pa, |
| 250 | uintptr_t max_va, int xlat_regime) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 251 | { |
Antonio Nino Diaz | 668d9ee | 2018-07-12 15:44:42 +0100 | [diff] [blame] | 252 | uint64_t mair, ttbr0, tcr; |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 253 | uintptr_t virtual_addr_space_size; |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 254 | |
| 255 | /* Set attributes in the right indices of the MAIR. */ |
| 256 | mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); |
| 257 | mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); |
| 258 | mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); |
| 259 | |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 260 | /* |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 261 | * Limit the input address ranges and memory region sizes translated |
| 262 | * using TTBR0 to the given virtual address space size. |
| 263 | */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 264 | assert(max_va < ((uint64_t)UINTPTR_MAX)); |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 265 | |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 266 | virtual_addr_space_size = (uintptr_t)max_va + 1U; |
Sathees Balya | 7415597 | 2019-01-25 11:36:01 +0000 | [diff] [blame] | 267 | |
| 268 | assert(virtual_addr_space_size >= |
| 269 | xlat_get_min_virt_addr_space_size()); |
| 270 | assert(virtual_addr_space_size <= MAX_VIRT_ADDR_SPACE_SIZE); |
| 271 | assert(IS_POWER_OF_TWO(virtual_addr_space_size)); |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 272 | |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 273 | /* |
Sandrine Bailleux | 12e8644 | 2017-07-19 10:11:13 +0100 | [diff] [blame] | 274 | * __builtin_ctzll(0) is undefined but here we are guaranteed that |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 275 | * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. |
| 276 | */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 277 | int t0sz = 64 - __builtin_ctzll(virtual_addr_space_size); |
| 278 | |
Antonio Nino Diaz | 37f97a5 | 2019-03-27 11:10:31 +0000 | [diff] [blame] | 279 | tcr = (uint64_t)t0sz << TCR_T0SZ_SHIFT; |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 280 | |
| 281 | /* |
| 282 | * Set the cacheability and shareability attributes for memory |
| 283 | * associated with translation table walks. |
| 284 | */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 285 | if ((flags & XLAT_TABLE_NC) != 0U) { |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 286 | /* Inner & outer non-cacheable non-shareable. */ |
| 287 | tcr |= TCR_SH_NON_SHAREABLE | |
| 288 | TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; |
| 289 | } else { |
| 290 | /* Inner & outer WBWA & shareable. */ |
| 291 | tcr |= TCR_SH_INNER_SHAREABLE | |
| 292 | TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; |
| 293 | } |
| 294 | |
Sandrine Bailleux | c5b6377 | 2017-05-31 13:31:48 +0100 | [diff] [blame] | 295 | /* |
| 296 | * It is safer to restrict the max physical address accessible by the |
| 297 | * hardware as much as possible. |
| 298 | */ |
Antonio Nino Diaz | bafc753 | 2017-10-25 11:53:25 +0100 | [diff] [blame] | 299 | unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa); |
Sandrine Bailleux | c5b6377 | 2017-05-31 13:31:48 +0100 | [diff] [blame] | 300 | |
Antonio Nino Diaz | 9d596c4 | 2018-07-12 15:43:07 +0100 | [diff] [blame] | 301 | if (xlat_regime == EL1_EL0_REGIME) { |
| 302 | /* |
| 303 | * TCR_EL1.EPD1: Disable translation table walk for addresses |
| 304 | * that are translated using TTBR1_EL1. |
| 305 | */ |
| 306 | tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 307 | } else if (xlat_regime == EL2_REGIME) { |
| 308 | tcr |= TCR_EL2_RES1 | (tcr_ps_bits << TCR_EL2_PS_SHIFT); |
Antonio Nino Diaz | 9d596c4 | 2018-07-12 15:43:07 +0100 | [diff] [blame] | 309 | } else { |
| 310 | assert(xlat_regime == EL3_REGIME); |
| 311 | tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); |
| 312 | } |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 313 | |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 314 | /* Set TTBR bits as well */ |
Antonio Nino Diaz | 668d9ee | 2018-07-12 15:44:42 +0100 | [diff] [blame] | 315 | ttbr0 = (uint64_t) base_table; |
| 316 | |
Antonio Nino Diaz | c326c34 | 2019-01-11 11:20:10 +0000 | [diff] [blame] | 317 | if (is_armv8_2_ttcnp_present()) { |
| 318 | /* Enable CnP bit so as to share page tables with all PEs. */ |
| 319 | ttbr0 |= TTBR_CNP_BIT; |
| 320 | } |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 321 | |
Antonio Nino Diaz | 67f799e | 2018-07-15 16:42:01 +0100 | [diff] [blame] | 322 | params[MMU_CFG_MAIR] = mair; |
| 323 | params[MMU_CFG_TCR] = tcr; |
| 324 | params[MMU_CFG_TTBR0] = ttbr0; |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 325 | } |