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Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01001/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __EL3_COMMON_MACROS_S__
32#define __EL3_COMMON_MACROS_S__
33
34#include <arch.h>
35#include <asm_macros.S>
36
37 /*
38 * Helper macro to initialise EL3 registers we care about.
39 */
40 .macro el3_arch_init_common _exception_vectors
41 /* ---------------------------------------------------------------------
42 * Enable the instruction cache, stack pointer and data access alignment
43 * checks
44 * ---------------------------------------------------------------------
45 */
46 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
47 mrs x0, sctlr_el3
48 orr x0, x0, x1
49 msr sctlr_el3, x0
50 isb
51
52#if IMAGE_BL31
53 /* ---------------------------------------------------------------------
54 * Initialise the per-cpu cache pointer to the CPU.
55 * This is done early to enable crash reporting to have access to crash
56 * stack. Since crash reporting depends on cpu_data to report the
57 * unhandled exception, not doing so can lead to recursive exceptions
58 * due to a NULL TPIDR_EL3.
59 * ---------------------------------------------------------------------
60 */
61 bl init_cpu_data_ptr
62#endif /* IMAGE_BL31 */
63
64 /* ---------------------------------------------------------------------
65 * Set the exception vectors.
66 * ---------------------------------------------------------------------
67 */
68 adr x0, \_exception_vectors
69 msr vbar_el3, x0
70 isb
71
72 /* ---------------------------------------------------------------------
73 * Enable the SError interrupt now that the exception vectors have been
74 * setup.
75 * ---------------------------------------------------------------------
76 */
77 msr daifclr, #DAIF_ABT_BIT
78
79 /* ---------------------------------------------------------------------
80 * The initial state of the Architectural feature trap register
81 * (CPTR_EL3) is unknown and it must be set to a known state. All
82 * feature traps are disabled. Some bits in this register are marked as
83 * reserved and should not be modified.
84 *
85 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
86 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
87 *
88 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap
89 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
90 * access to trace functionality is not supported, this bit is RES0.
91 *
92 * CPTR_EL3.TFP: This causes instructions that access the registers
93 * associated with Floating Point and Advanced SIMD execution to trap
94 * to EL3 when executed from any exception level, unless trapped to EL1
95 * or EL2.
96 * ---------------------------------------------------------------------
97 */
98 mrs x0, cptr_el3
99 bic w0, w0, #TCPAC_BIT
100 bic w0, w0, #TTA_BIT
101 bic w0, w0, #TFP_BIT
102 msr cptr_el3, x0
103 .endm
104
105/* -----------------------------------------------------------------------------
106 * This is the super set of actions that need to be performed during a cold boot
107 * or a warm boot in EL3. This code is shared by BL1 and BL3-1.
108 *
109 * This macro will always perform reset handling, architectural initialisations
110 * and stack setup. The rest of the actions are optional because they might not
111 * be needed, depending on the context in which this macro is called. This is
112 * why this macro is parameterised ; each parameter allows to enable/disable
113 * some actions.
114 *
115 * _set_endian:
116 * Whether the macro needs to configure the endianness of data accesses.
117 *
118 * _warm_boot_mailbox:
119 * Whether the macro needs to detect the type of boot (cold/warm). The
120 * detection is based on the platform entrypoint address : if it is zero
121 * then it is a cold boot, otherwise it is a warm boot. In the latter case,
122 * this macro jumps on the platform entrypoint address.
123 *
124 * _secondary_cold_boot:
125 * Whether the macro needs to identify the CPU that is calling it: primary
126 * CPU or secondary CPU. The primary CPU will be allowed to carry on with
127 * the platform initialisations, while the secondaries will be put in a
128 * platform-specific state in the meantime.
129 *
130 * If the caller knows this macro will only be called by the primary CPU
131 * then this parameter can be defined to 0 to skip this step.
132 *
133 * _init_memory:
134 * Whether the macro needs to initialise the memory.
135 *
136 * _init_c_runtime:
137 * Whether the macro needs to initialise the C runtime environment.
138 *
139 * _exception_vectors:
140 * Address of the exception vectors to program in the VBAR_EL3 register.
141 * -----------------------------------------------------------------------------
142 */
143 .macro el3_entrypoint_common \
144 _set_endian, _warm_boot_mailbox, _secondary_cold_boot, \
145 _init_memory, _init_c_runtime, _exception_vectors
146
147 .if \_set_endian
148 /* -------------------------------------------------------------
149 * Set the CPU endianness before doing anything that might
150 * involve memory reads or writes.
151 * -------------------------------------------------------------
152 */
153 mrs x0, sctlr_el3
154 bic x0, x0, #SCTLR_EE_BIT
155 msr sctlr_el3, x0
156 isb
157 .endif /* _set_endian */
158
159 .if \_warm_boot_mailbox
160 /* -------------------------------------------------------------
161 * This code will be executed for both warm and cold resets.
162 * Now is the time to distinguish between the two.
163 * Query the platform entrypoint address and if it is not zero
164 * then it means it is a warm boot so jump to this address.
165 * -------------------------------------------------------------
166 */
Soby Mathew3700a922015-07-13 11:21:11 +0100167 bl plat_get_my_entrypoint
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100168 cbz x0, do_cold_boot
169 br x0
170
171 do_cold_boot:
172 .endif /* _warm_boot_mailbox */
173
174 .if \_secondary_cold_boot
175 /* -------------------------------------------------------------
176 * It is a cold boot.
177 * The primary CPU will set up the platform while the
178 * secondaries are placed in a platform-specific state until the
179 * primary CPU performs the necessary actions to bring them out
180 * of that state and allows entry into the OS.
181 * -------------------------------------------------------------
182 */
Soby Mathew3700a922015-07-13 11:21:11 +0100183 bl plat_is_my_cpu_primary
Soby Matheweb3bbf12015-06-08 12:32:50 +0100184 cbnz w0, do_primary_cold_boot
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100185
186 /* This is a cold boot on a secondary CPU */
187 bl plat_secondary_cold_boot_setup
188 /* plat_secondary_cold_boot_setup() is not supposed to return */
189 secondary_panic:
190 b secondary_panic
191
192 do_primary_cold_boot:
193 .endif /* _secondary_cold_boot */
194
195 /* ---------------------------------------------------------------------
196 * Perform any processor specific actions upon reset e.g. cache, TLB
197 * invalidations etc.
198 * ---------------------------------------------------------------------
199 */
200 bl reset_handler
201
202 el3_arch_init_common \_exception_vectors
203
204 .if \_init_memory
205 bl platform_mem_init
206 .endif /* _init_memory */
207
208 /* ---------------------------------------------------------------------
209 * Init C runtime environment:
210 * - Zero-initialise the NOBITS sections. There are 2 of them:
211 * - the .bss section;
212 * - the coherent memory section (if any).
213 * - Relocate the data section from ROM to RAM, if required.
214 * ---------------------------------------------------------------------
215 */
216 .if \_init_c_runtime
Achin Guptae9c4a642015-09-11 16:03:13 +0100217#if IMAGE_BL31
218 /* -------------------------------------------------------------
219 * Invalidate the RW memory used by the BL31 image. This
220 * includes the data and NOBITS sections. This is done to
221 * safeguard against possible corruption of this memory by
222 * dirty cache lines in a system cache as a result of use by
223 * an earlier boot loader stage.
224 * -------------------------------------------------------------
225 */
226 adr x0, __RW_START__
227 adr x1, __RW_END__
228 sub x1, x1, x0
229 bl inv_dcache_range
230#endif /* IMAGE_BL31 */
231
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100232 ldr x0, =__BSS_START__
233 ldr x1, =__BSS_SIZE__
234 bl zeromem16
235
236#if USE_COHERENT_MEM
237 ldr x0, =__COHERENT_RAM_START__
238 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
239 bl zeromem16
240#endif
241
Sandrine Bailleux4534c642015-06-24 15:26:39 +0100242#if IMAGE_BL1
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100243 ldr x0, =__DATA_RAM_START__
244 ldr x1, =__DATA_ROM_START__
245 ldr x2, =__DATA_SIZE__
246 bl memcpy16
247#endif
248 .endif /* _init_c_runtime */
249
250#if IMAGE_BL31
251 /* ---------------------------------------------------------------------
252 * Use SP_EL0 for the C runtime stack.
253 * ---------------------------------------------------------------------
254 */
255 msr spsel, #0
256#endif /* IMAGE_BL31 */
257
258 /* ---------------------------------------------------------------------
259 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
260 * the MMU is enabled. There is no risk of reading stale stack memory
261 * after enabling the MMU as only the primary CPU is running at the
262 * moment.
263 * ---------------------------------------------------------------------
264 */
Soby Mathew3700a922015-07-13 11:21:11 +0100265 bl plat_set_my_stack
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100266 .endm
267
268#endif /* __EL3_COMMON_MACROS_S__ */