Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 31 | #include <arch_helpers.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 32 | #include <assert.h> |
| 33 | #include <debug.h> |
| 34 | #include <mmio.h> |
| 35 | #include <memctrl.h> |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 36 | #include <string.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 37 | #include <tegra_def.h> |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 38 | #include <xlat_tables.h> |
| 39 | |
| 40 | extern void zeromem16(void *mem, unsigned int length); |
| 41 | |
| 42 | #define TEGRA_GPU_RESET_REG_OFFSET 0x28c |
| 43 | #define GPU_RESET_BIT (1 << 24) |
| 44 | |
| 45 | /* Video Memory base and size (live values) */ |
| 46 | static uintptr_t video_mem_base; |
| 47 | static uint64_t video_mem_size; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 48 | |
| 49 | /* |
| 50 | * Init SMMU. |
| 51 | */ |
| 52 | void tegra_memctrl_setup(void) |
| 53 | { |
| 54 | /* |
| 55 | * Setup the Memory controller to allow only secure accesses to |
| 56 | * the TZDRAM carveout |
| 57 | */ |
| 58 | INFO("Configuring SMMU\n"); |
| 59 | |
| 60 | /* allow translations for all MC engines */ |
| 61 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0, |
| 62 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 63 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_1_0, |
| 64 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 65 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_2_0, |
| 66 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 67 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_3_0, |
| 68 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 69 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_4_0, |
| 70 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 71 | |
| 72 | tegra_mc_write_32(MC_SMMU_ASID_SECURITY_0, MC_SMMU_ASID_SECURITY); |
| 73 | |
| 74 | tegra_mc_write_32(MC_SMMU_TLB_CONFIG_0, MC_SMMU_TLB_CONFIG_0_RESET_VAL); |
| 75 | tegra_mc_write_32(MC_SMMU_PTC_CONFIG_0, MC_SMMU_PTC_CONFIG_0_RESET_VAL); |
| 76 | |
| 77 | /* flush PTC and TLB */ |
| 78 | tegra_mc_write_32(MC_SMMU_PTC_FLUSH_0, MC_SMMU_PTC_FLUSH_ALL); |
| 79 | (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ |
| 80 | tegra_mc_write_32(MC_SMMU_TLB_FLUSH_0, MC_SMMU_TLB_FLUSH_ALL); |
| 81 | |
| 82 | /* enable SMMU */ |
| 83 | tegra_mc_write_32(MC_SMMU_CONFIG_0, |
| 84 | MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE); |
| 85 | (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 86 | |
| 87 | /* video memory carveout */ |
| 88 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, video_mem_base); |
| 89 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | /* |
| 93 | * Secure the BL31 DRAM aperture. |
| 94 | * |
| 95 | * phys_base = physical base of TZDRAM aperture |
| 96 | * size_in_bytes = size of aperture in bytes |
| 97 | */ |
| 98 | void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 99 | { |
| 100 | /* |
| 101 | * Setup the Memory controller to allow only secure accesses to |
| 102 | * the TZDRAM carveout |
| 103 | */ |
| 104 | INFO("Configuring TrustZone DRAM Memory Carveout\n"); |
| 105 | |
| 106 | tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base); |
| 107 | tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); |
| 108 | } |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 109 | |
| 110 | /* |
| 111 | * Program the Video Memory carveout region |
| 112 | * |
| 113 | * phys_base = physical base of aperture |
| 114 | * size_in_bytes = size of aperture in bytes |
| 115 | */ |
| 116 | void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 117 | { |
| 118 | uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20); |
| 119 | uintptr_t vmem_end_new = phys_base + size_in_bytes; |
| 120 | uint32_t regval; |
| 121 | |
| 122 | /* |
| 123 | * The GPU is the user of the Video Memory region. In order to |
| 124 | * transition to the new memory region smoothly, we program the |
| 125 | * new base/size ONLY if the GPU is in reset mode. |
| 126 | */ |
| 127 | regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); |
| 128 | if ((regval & GPU_RESET_BIT) == 0) { |
| 129 | ERROR("GPU not in reset! Video Memory setup failed\n"); |
| 130 | return; |
| 131 | } |
| 132 | |
| 133 | /* |
| 134 | * Setup the Memory controller to restrict CPU accesses to the Video |
| 135 | * Memory region |
| 136 | */ |
| 137 | INFO("Configuring Video Memory Carveout\n"); |
| 138 | |
| 139 | /* |
| 140 | * Configure Memory Controller directly for the first time. |
| 141 | */ |
| 142 | if (video_mem_base == 0) |
| 143 | goto done; |
| 144 | |
| 145 | /* |
| 146 | * Clear the old regions now being exposed. The following cases |
| 147 | * can occur - |
| 148 | * |
| 149 | * 1. clear whole old region (no overlap with new region) |
| 150 | * 2. clear old sub-region below new base |
| 151 | * 3. clear old sub-region above new end |
| 152 | */ |
| 153 | INFO("Cleaning previous Video Memory Carveout\n"); |
| 154 | |
| 155 | disable_mmu_el3(); |
| 156 | if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) |
| 157 | zeromem16((void *)video_mem_base, video_mem_size << 20); |
| 158 | else if (video_mem_base < phys_base) |
| 159 | zeromem16((void *)video_mem_base, phys_base - video_mem_base); |
| 160 | else if (vmem_end_old > vmem_end_new) |
| 161 | zeromem16((void *)vmem_end_new, vmem_end_old - vmem_end_new); |
| 162 | enable_mmu_el3(0); |
| 163 | |
| 164 | done: |
| 165 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, phys_base); |
| 166 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); |
| 167 | |
| 168 | /* store new values */ |
| 169 | video_mem_base = phys_base; |
| 170 | video_mem_size = size_in_bytes >> 20; |
| 171 | } |