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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handley0cdebbd2015-03-30 17:15:16 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Juan Castilloa08a5e72015-05-19 11:54:12 +010034#include <auth_mod.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010035#include <bl_common.h>
Vikram Kanigirida567432014-04-15 18:08:08 +010036#include <debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010037#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010038#include <platform_def.h>
Dan Handleybcd60ba2014-04-17 18:53:42 +010039#include "bl1_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
41/*******************************************************************************
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010042 * Runs BL2 from the given entry point. It results in dropping the
43 * exception level
44 ******************************************************************************/
Vikram Kanigirida567432014-04-15 18:08:08 +010045static void __dead2 bl1_run_bl2(entry_point_info_t *bl2_ep)
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010046{
Vikram Kanigiriceb0d0f2015-07-23 11:16:28 +010047 /* Check bl2 security state is expected as secure */
48 assert(GET_SECURITY_STATE(bl2_ep->h.attr) == SECURE);
49 /* Check NS Bit is also set as secure */
50 assert(!(read_scr_el3() & SCR_NS_BIT));
51
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010052 bl1_arch_next_el_setup();
53
54 /* Tell next EL what we want done */
55 bl2_ep->args.arg0 = RUN_IMAGE;
56
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010057 write_spsr_el3(bl2_ep->spsr);
Vikram Kanigirida567432014-04-15 18:08:08 +010058 write_elr_el3(bl2_ep->pc);
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010059
60 eret(bl2_ep->args.arg0,
61 bl2_ep->args.arg1,
62 bl2_ep->args.arg2,
63 bl2_ep->args.arg3,
64 bl2_ep->args.arg4,
65 bl2_ep->args.arg5,
66 bl2_ep->args.arg6,
67 bl2_ep->args.arg7);
68}
69
Sandrine Bailleux467d0572014-06-24 14:02:34 +010070/*******************************************************************************
71 * The next function has a weak definition. Platform specific code can override
72 * it if it wishes to.
73 ******************************************************************************/
74#pragma weak bl1_init_bl2_mem_layout
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010075
76/*******************************************************************************
Sandrine Bailleux467d0572014-06-24 14:02:34 +010077 * Function that takes a memory layout into which BL2 has been loaded and
78 * populates a new memory layout for BL2 that ensures that BL1's data sections
79 * resident in secure RAM are not visible to BL2.
80 ******************************************************************************/
81void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
82 meminfo_t *bl2_mem_layout)
83{
84 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
85
86 assert(bl1_mem_layout != NULL);
87 assert(bl2_mem_layout != NULL);
88
89 /* Check that BL1's memory is lying outside of the free memory */
90 assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) ||
91 (BL1_RAM_BASE >= bl1_mem_layout->free_base + bl1_mem_layout->free_size));
92
93 /* Remove BL1 RW data from the scope of memory visible to BL2 */
94 *bl2_mem_layout = *bl1_mem_layout;
95 reserve_mem(&bl2_mem_layout->total_base,
96 &bl2_mem_layout->total_size,
97 BL1_RAM_BASE,
98 bl1_size);
99
100 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
101}
102
103/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100104 * Function to perform late architectural and platform specific initialization.
105 * It also locates and loads the BL2 raw binary image in the trusted DRAM. Only
106 * called by the primary cpu after a cold boot.
107 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
108 * loader etc.
109 ******************************************************************************/
110void bl1_main(void)
111{
Dan Handley91b624e2014-07-29 17:14:00 +0100112 /* Announce our arrival */
113 NOTICE(FIRMWARE_WELCOME_STR);
114 NOTICE("BL1: %s\n", version_string);
115 NOTICE("BL1: %s\n", build_message);
116
117 INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT);
118
Vikram Kanigirida567432014-04-15 18:08:08 +0100119 image_info_t bl2_image_info = { {0} };
120 entry_point_info_t bl2_ep = { {0} };
Dan Handleye2712bc2014-04-10 15:37:22 +0100121 meminfo_t *bl1_tzram_layout;
122 meminfo_t *bl2_tzram_layout = 0x0;
Vikram Kanigirida567432014-04-15 18:08:08 +0100123 int err;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100124
Dan Handley0cdebbd2015-03-30 17:15:16 +0100125#if DEBUG
126 unsigned long val;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127 /*
128 * Ensure that MMU/Caches and coherency are turned on
129 */
Dan Handley0cdebbd2015-03-30 17:15:16 +0100130 val = read_sctlr_el3();
Andrew Thoelke5e287b52015-06-11 14:12:14 +0100131 assert(val & SCTLR_M_BIT);
132 assert(val & SCTLR_C_BIT);
133 assert(val & SCTLR_I_BIT);
Dan Handley0cdebbd2015-03-30 17:15:16 +0100134 /*
135 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
136 * provided platform value
137 */
138 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
139 /*
140 * If CWG is zero, then no CWG information is available but we can
141 * at least check the platform value is less than the architectural
142 * maximum.
143 */
144 if (val != 0)
145 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
146 else
147 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
148#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100149
150 /* Perform remaining generic architectural setup from EL3 */
151 bl1_arch_setup();
152
153 /* Perform platform setup in BL1. */
154 bl1_platform_setup();
155
Vikram Kanigirida567432014-04-15 18:08:08 +0100156 SET_PARAM_HEAD(&bl2_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0);
157 SET_PARAM_HEAD(&bl2_ep, PARAM_EP, VERSION_1, 0);
158
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100159 /* Find out how much free trusted ram remains after BL1 load */
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +0000160 bl1_tzram_layout = bl1_plat_sec_mem_layout();
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100161
Juan Castillo3a66aca2015-04-13 17:36:19 +0100162 INFO("BL1: Loading BL2\n");
163
Juan Castillod227d8b2015-01-07 13:49:59 +0000164#if TRUSTED_BOARD_BOOT
165 /* Initialize authentication module */
Juan Castilloa08a5e72015-05-19 11:54:12 +0100166 auth_mod_init();
Juan Castillod227d8b2015-01-07 13:49:59 +0000167#endif /* TRUSTED_BOARD_BOOT */
168
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100169 /* Load the BL2 image */
Juan Castilloa08a5e72015-05-19 11:54:12 +0100170 err = load_auth_image(bl1_tzram_layout,
Juan Castillo3a66aca2015-04-13 17:36:19 +0100171 BL2_IMAGE_ID,
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100172 BL2_BASE,
173 &bl2_image_info,
174 &bl2_ep);
Juan Castilloa08a5e72015-05-19 11:54:12 +0100175
Vikram Kanigirida567432014-04-15 18:08:08 +0100176 if (err) {
177 /*
178 * TODO: print failure to load BL2 but also add a tzwdog timer
179 * which will reset the system eventually.
180 */
Dan Handley91b624e2014-07-29 17:14:00 +0100181 ERROR("Failed to load BL2 firmware.\n");
Vikram Kanigirida567432014-04-15 18:08:08 +0100182 panic();
183 }
Juan Castillod227d8b2015-01-07 13:49:59 +0000184
Achin Gupta4f6ad662013-10-25 09:08:21 +0100185 /*
186 * Create a new layout of memory for BL2 as seen by BL1 i.e.
187 * tell it the amount of total and free memory available.
188 * This layout is created at the first free address visible
189 * to BL2. BL2 will read the memory layout before using its
190 * memory for other purposes.
191 */
Dan Handleye2712bc2014-04-10 15:37:22 +0100192 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base;
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100193 bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100194
Vikram Kanigirida567432014-04-15 18:08:08 +0100195 bl1_plat_set_bl2_ep_info(&bl2_image_info, &bl2_ep);
196 bl2_ep.args.arg1 = (unsigned long)bl2_tzram_layout;
Dan Handley91b624e2014-07-29 17:14:00 +0100197 NOTICE("BL1: Booting BL2\n");
198 INFO("BL1: BL2 address = 0x%llx\n",
Vikram Kanigirida567432014-04-15 18:08:08 +0100199 (unsigned long long) bl2_ep.pc);
Dan Handley91b624e2014-07-29 17:14:00 +0100200 INFO("BL1: BL2 spsr = 0x%x\n", bl2_ep.spsr);
201 VERBOSE("BL1: BL2 memory layout address = 0x%llx\n",
202 (unsigned long long) bl2_tzram_layout);
203
Vikram Kanigirida567432014-04-15 18:08:08 +0100204 bl1_run_bl2(&bl2_ep);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100205
Achin Gupta4f6ad662013-10-25 09:08:21 +0100206 return;
207}
208
209/*******************************************************************************
210 * Temporary function to print the fact that BL2 has done its job and BL31 is
211 * about to be loaded. This is needed as long as printfs cannot be used
212 ******************************************************************************/
Vikram Kanigirida567432014-04-15 18:08:08 +0100213void display_boot_progress(entry_point_info_t *bl31_ep_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100214{
Dan Handley91b624e2014-07-29 17:14:00 +0100215 NOTICE("BL1: Booting BL3-1\n");
216 INFO("BL1: BL3-1 address = 0x%llx\n",
217 (unsigned long long)bl31_ep_info->pc);
218 INFO("BL1: BL3-1 spsr = 0x%llx\n",
219 (unsigned long long)bl31_ep_info->spsr);
220 INFO("BL1: BL3-1 params address = 0x%llx\n",
221 (unsigned long long)bl31_ep_info->args.arg0);
222 INFO("BL1: BL3-1 plat params address = 0x%llx\n",
223 (unsigned long long)bl31_ep_info->args.arg1);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100224}