developer | b23acff | 2021-06-20 16:48:08 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, MediaTek Inc. All rights reserved. \ |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
| 8 | #include <mtk_ptp3_common.h> |
| 9 | |
| 10 | #define PTP3_CORE_OFT(core) (0x800 * (core)) |
| 11 | |
| 12 | /************************************************ |
| 13 | * Central control |
| 14 | ************************************************/ |
| 15 | static unsigned int ptp3_cfg1[NR_PTP3_CFG1_DATA][NR_PTP3_CFG] = { |
| 16 | {0x0C53A2A0, 0x1000}, |
| 17 | {0x0C53A2A4, 0x1000} |
| 18 | }; |
| 19 | |
| 20 | static unsigned int ptp3_cfg2[NR_PTP3_CFG2_DATA][NR_PTP3_CFG] = { |
| 21 | {0x0C530404, 0x3A1000}, |
| 22 | {0x0C530428, 0x13E0408}, |
| 23 | {0x0C530434, 0xB22800}, |
| 24 | {0x0C53043C, 0x750}, |
| 25 | {0x0C530440, 0x0222c4cc} |
| 26 | }; |
| 27 | |
| 28 | static unsigned int ptp3_cfg3[NR_PTP3_CFG] = {0x0C530400, 0x2D80}; |
| 29 | static unsigned int ptp3_cfg3_ext[NR_PTP3_CFG] = {0x0C530400, 0xC00}; |
| 30 | |
| 31 | static void ptp3_init(unsigned int core) |
| 32 | { |
| 33 | unsigned int i, addr, value; |
| 34 | |
| 35 | if (core < PTP3_CFG_CPU_START_ID_B) { |
| 36 | ptp3_clrsetbits(ptp3_cfg1[0][PTP3_CFG_ADDR], PTP3_CFG1_MASK, |
| 37 | ptp3_cfg1[0][PTP3_CFG_VALUE]); |
| 38 | } else { |
| 39 | ptp3_clrsetbits(ptp3_cfg1[1][PTP3_CFG_ADDR], PTP3_CFG1_MASK, |
| 40 | ptp3_cfg1[1][PTP3_CFG_VALUE]); |
| 41 | } |
| 42 | |
| 43 | if (core < PTP3_CFG_CPU_START_ID_B) { |
| 44 | for (i = 0; i < NR_PTP3_CFG2_DATA; i++) { |
| 45 | addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + |
| 46 | PTP3_CORE_OFT(core); |
| 47 | value = ptp3_cfg2[i][PTP3_CFG_VALUE]; |
| 48 | |
| 49 | ptp3_write(addr, value); |
| 50 | } |
| 51 | } else { |
| 52 | for (i = 0; i < NR_PTP3_CFG2_DATA; i++) { |
| 53 | addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + |
| 54 | PTP3_CORE_OFT(core); |
| 55 | |
| 56 | if (i == 2) { |
| 57 | value = ptp3_cfg2[i][PTP3_CFG_VALUE] + 0x5E0; |
| 58 | } else { |
| 59 | value = ptp3_cfg2[i][PTP3_CFG_VALUE]; |
| 60 | } |
| 61 | ptp3_write(addr, value); |
| 62 | } |
| 63 | } |
| 64 | |
| 65 | if (core < PTP3_CFG_CPU_START_ID_B) { |
| 66 | addr = ptp3_cfg3[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); |
| 67 | value = ptp3_cfg3[PTP3_CFG_VALUE]; |
| 68 | |
| 69 | ptp3_write(addr, value & PTP3_CFG3_MASK1); |
| 70 | ptp3_write(addr, value & PTP3_CFG3_MASK2); |
| 71 | ptp3_write(addr, value & PTP3_CFG3_MASK3); |
| 72 | } else { |
| 73 | addr = ptp3_cfg3_ext[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); |
| 74 | value = ptp3_cfg3_ext[PTP3_CFG_VALUE]; |
| 75 | |
| 76 | ptp3_write(addr, value & PTP3_CFG3_MASK1); |
| 77 | ptp3_write(addr, value & PTP3_CFG3_MASK2); |
| 78 | ptp3_write(addr, value & PTP3_CFG3_MASK3); |
| 79 | } |
| 80 | } |
| 81 | |
| 82 | void pdp_proc_ARM_write(unsigned int pdp_n) |
| 83 | { |
| 84 | unsigned long v = 0; |
| 85 | |
| 86 | dsb(); |
| 87 | __asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v)); |
| 88 | v |= (UL(0x0) << 52); |
| 89 | v |= (UL(0x1) << 53); |
| 90 | v |= (UL(0x0) << 54); |
| 91 | v |= (UL(0x0) << 48); |
| 92 | v |= (UL(0x1) << 49); |
| 93 | __asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v)); |
| 94 | dsb(); |
| 95 | } |
| 96 | |
| 97 | void pdp_init(unsigned int pdp_cpu, unsigned int en) |
| 98 | { |
| 99 | if ((pdp_cpu >= PTP3_CFG_CPU_START_ID_B) && |
| 100 | (pdp_cpu < NR_PTP3_CFG_CPU)) { |
| 101 | pdp_proc_ARM_write(pdp_cpu); |
| 102 | } |
| 103 | } |
| 104 | |
| 105 | static void dt_proc_ARM_write(unsigned int dt_n) |
| 106 | { |
| 107 | unsigned long v = 0; |
| 108 | |
| 109 | dsb(); |
| 110 | __asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v)); |
| 111 | v |= (UL(0x0) << 33); |
| 112 | v |= (UL(0x0) << 32); |
| 113 | __asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v)); |
| 114 | dsb(); |
| 115 | } |
| 116 | |
| 117 | void dt_init(unsigned int dt_cpu, unsigned int en) |
| 118 | { |
| 119 | if ((dt_cpu >= PTP3_CFG_CPU_START_ID_B) && |
| 120 | (dt_cpu < NR_PTP3_CFG_CPU)) { |
| 121 | dt_proc_ARM_write(dt_cpu); |
| 122 | } |
| 123 | } |
| 124 | void ptp3_core_init(unsigned int core) |
| 125 | { |
| 126 | /* init for ptp3 */ |
| 127 | ptp3_init(core); |
| 128 | /* init for pdp */ |
| 129 | pdp_init(core, 1); |
| 130 | /* init for dt */ |
| 131 | dt_init(core, 1); |
| 132 | } |
| 133 | |
| 134 | void ptp3_core_unInit(unsigned int core) |
| 135 | { |
| 136 | /* TBD */ |
| 137 | } |