XiaoDong Huang | 83f79a8 | 2019-06-13 10:55:50 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <platform_def.h> |
| 8 | |
| 9 | #include <arch_helpers.h> |
| 10 | #include <common/debug.h> |
| 11 | #include <drivers/console.h> |
| 12 | #include <drivers/delay_timer.h> |
| 13 | #include <lib/mmio.h> |
| 14 | |
| 15 | #include <ddr_parameter.h> |
| 16 | #include <platform_def.h> |
| 17 | #include <pmu.h> |
| 18 | #include <px30_def.h> |
| 19 | #include <soc.h> |
| 20 | #include <rockchip_sip_svc.h> |
| 21 | |
| 22 | /* Aggregate of all devices in the first GB */ |
| 23 | #define PX30_DEV_RNG0_BASE 0xff000000 |
| 24 | #define PX30_DEV_RNG0_SIZE 0x00ff0000 |
| 25 | |
| 26 | const mmap_region_t plat_rk_mmap[] = { |
| 27 | MAP_REGION_FLAT(PX30_DEV_RNG0_BASE, PX30_DEV_RNG0_SIZE, |
| 28 | MT_DEVICE | MT_RW | MT_SECURE), |
| 29 | MAP_REGION_FLAT(SHARE_MEM_BASE, SHARE_MEM_SIZE, |
| 30 | MT_DEVICE | MT_RW | MT_SECURE), |
| 31 | MAP_REGION_FLAT(DDR_PARAM_BASE, DDR_PARAM_SIZE, |
| 32 | MT_DEVICE | MT_RW | MT_SECURE), |
| 33 | { 0 } |
| 34 | }; |
| 35 | |
| 36 | /* The RockChip power domain tree descriptor */ |
| 37 | const unsigned char rockchip_power_domain_tree_desc[] = { |
| 38 | /* No of root nodes */ |
| 39 | PLATFORM_SYSTEM_COUNT, |
| 40 | /* No of children for the root node */ |
| 41 | PLATFORM_CLUSTER_COUNT, |
| 42 | /* No of children for the first cluster node */ |
| 43 | PLATFORM_CLUSTER0_CORE_COUNT, |
| 44 | }; |
| 45 | |
| 46 | void clk_gate_con_save(uint32_t *clkgt_save) |
| 47 | { |
| 48 | uint32_t i, j; |
| 49 | |
| 50 | for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) |
| 51 | clkgt_save[i] = |
| 52 | mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); |
| 53 | j = i; |
| 54 | for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++) |
| 55 | clkgt_save[j] = |
| 56 | mmio_read_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i)); |
| 57 | } |
| 58 | |
| 59 | void clk_gate_con_restore(uint32_t *clkgt_save) |
| 60 | { |
| 61 | uint32_t i, j; |
| 62 | |
| 63 | for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) |
| 64 | mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), |
| 65 | WITH_16BITS_WMSK(clkgt_save[i])); |
| 66 | |
| 67 | j = i; |
| 68 | for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++) |
| 69 | mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i), |
| 70 | WITH_16BITS_WMSK(clkgt_save[j])); |
| 71 | } |
| 72 | |
| 73 | void clk_gate_con_disable(void) |
| 74 | { |
| 75 | uint32_t i; |
| 76 | |
| 77 | for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) |
| 78 | mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), |
| 79 | 0xffff0000); |
| 80 | |
| 81 | for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++) |
| 82 | mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i), |
| 83 | 0xffff0000); |
| 84 | } |
| 85 | |
| 86 | void secure_timer_init(void) |
| 87 | { |
| 88 | mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, |
| 89 | TIMER_DIS); |
| 90 | |
| 91 | mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff); |
| 92 | mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff); |
| 93 | |
| 94 | /* auto reload & enable the timer */ |
| 95 | mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, |
| 96 | TIMER_EN | TIMER_FMODE); |
| 97 | } |
| 98 | |
| 99 | static void sgrf_init(void) |
| 100 | { |
| 101 | uint32_t i, val; |
| 102 | struct param_ddr_usage usg; |
| 103 | |
| 104 | /* general secure regions */ |
| 105 | usg = ddr_region_usage_parse(DDR_PARAM_BASE, |
| 106 | PLAT_MAX_DDR_CAPACITY_MB); |
| 107 | for (i = 0; i < usg.s_nr; i++) { |
| 108 | /* enable secure */ |
| 109 | val = mmio_read_32(FIREWALL_DDR_BASE + |
| 110 | FIREWALL_DDR_FW_DDR_CON_REG); |
| 111 | val |= BIT(7 - i); |
| 112 | mmio_write_32(FIREWALL_DDR_BASE + |
| 113 | FIREWALL_DDR_FW_DDR_CON_REG, val); |
| 114 | /* map top and base */ |
| 115 | mmio_write_32(FIREWALL_DDR_BASE + |
| 116 | FIREWALL_DDR_FW_DDR_RGN(7 - i), |
| 117 | RG_MAP_SECURE(usg.s_top[i], usg.s_base[i])); |
| 118 | } |
| 119 | |
| 120 | /* set ddr rgn0_top and rga0_top as 0 */ |
| 121 | mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); |
| 122 | |
| 123 | /* set all slave ip into no-secure, except stimer */ |
| 124 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS); |
| 125 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS); |
| 126 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS); |
| 127 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS); |
| 128 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000); |
| 129 | |
| 130 | /* set master crypto to no-secure, dcf to secure */ |
| 131 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003); |
| 132 | |
| 133 | /* set DMAC into no-secure */ |
| 134 | mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS); |
| 135 | mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0); |
| 136 | mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16); |
| 137 | mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS); |
| 138 | |
| 139 | /* soft reset dma before use */ |
| 140 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ); |
| 141 | udelay(5); |
| 142 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS); |
| 143 | } |
| 144 | |
| 145 | static void soc_reset_config_all(void) |
| 146 | { |
| 147 | uint32_t tmp; |
| 148 | |
| 149 | /* tsadc and wdt can trigger a first rst */ |
| 150 | tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); |
| 151 | tmp |= CRU_GLB_RST_TSADC_FST | CRU_GLB_RST_WDT_FST; |
| 152 | mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); |
| 153 | return; |
| 154 | tmp = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(3)); |
| 155 | tmp &= ~(PMUGRF_FAILSAFE_SHTDN_TSADC | PMUGRF_FAILSAFE_SHTDN_WDT); |
| 156 | mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(3), tmp); |
| 157 | |
| 158 | /* wdt pin rst eable */ |
| 159 | mmio_write_32(GRF_BASE + GRF_SOC_CON(2), |
| 160 | BIT_WITH_WMSK(GRF_SOC_CON2_NSWDT_RST_EN)); |
| 161 | } |
| 162 | |
| 163 | void px30_soc_reset_config(void) |
| 164 | { |
| 165 | uint32_t tmp; |
| 166 | |
| 167 | /* enable soc ip rst hold time cfg */ |
| 168 | tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); |
| 169 | tmp |= BIT(CRU_GLB_RST_TSADC_EXT) | BIT(CRU_GLB_RST_WDT_EXT); |
| 170 | mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); |
| 171 | /* soc ip rst hold time, 24m */ |
| 172 | tmp = mmio_read_32(CRU_BASE + CRU_GLB_CNT_TH); |
| 173 | tmp &= ~CRU_GLB_CNT_RST_MSK; |
| 174 | tmp |= (CRU_GLB_CNT_RST_1MS / 2); |
| 175 | mmio_write_32(CRU_BASE + CRU_GLB_CNT_TH, tmp); |
| 176 | |
| 177 | mmio_write_32(PMUSGRF_BASE + PMUSGRF_SOC_CON(0), |
| 178 | BIT_WITH_WMSK(PMUSGRF_RSTOUT_FST) | |
| 179 | BIT_WITH_WMSK(PMUSGRF_RSTOUT_TSADC) | |
| 180 | BIT_WITH_WMSK(PMUSGRF_RSTOUT_WDT)); |
| 181 | |
| 182 | /* rst_out pulse time */ |
| 183 | mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(2), |
| 184 | PMUGRF_SOC_CON2_MAX_341US | PMUGRF_SOC_CON2_US_WMSK); |
| 185 | |
| 186 | soc_reset_config_all(); |
| 187 | } |
| 188 | |
| 189 | void plat_rockchip_soc_init(void) |
| 190 | { |
| 191 | secure_timer_init(); |
| 192 | sgrf_init(); |
| 193 | } |