blob: 4672cbc061623e07e503ae2b71ec4b460680709f [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dimitris Papastamos914757c2018-03-12 14:47:09 +00002 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
Dan Handleyea596682015-04-01 17:34:24 +01006#ifndef __CPU_MACROS_S__
7#define __CPU_MACROS_S__
Achin Gupta4f6ad662013-10-25 09:08:21 +01008
9#include <arch.h>
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000010#include <errata_report.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010011
Soby Mathewc704cbc2014-08-14 11:33:56 +010012#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
13 (MIDR_PN_MASK << MIDR_PN_SHIFT)
Achin Gupta4f6ad662013-10-25 09:08:21 +010014
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +000015/* The number of CPU operations allowed */
16#define CPU_MAX_PWR_DWN_OPS 2
17
18/* Special constant to specify that CPU has no reset function */
19#define CPU_NO_RESET_FUNC 0
20
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010021#define CPU_NO_EXTRA1_FUNC 0
22#define CPU_NO_EXTRA2_FUNC 0
23
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +000024/* Word size for 64-bit CPUs */
25#define CPU_WORD_SIZE 8
26
Roberto Vargase0e99462017-10-30 14:43:43 +000027#if defined(IMAGE_BL1) || defined(IMAGE_BL31) ||(defined(IMAGE_BL2) && BL2_AT_EL3)
28#define IMAGE_AT_EL3
29#endif
30
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000031/*
32 * Whether errata status needs reporting. Errata status is printed in debug
33 * builds for both BL1 and BL31 images.
34 */
35#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG
36# define REPORT_ERRATA 1
37#else
38# define REPORT_ERRATA 0
39#endif
40
Roberto Vargas67762d92018-05-01 09:54:54 +010041
42 .equ CPU_MIDR_SIZE, CPU_WORD_SIZE
43 .equ CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE
44 .equ CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE
45 .equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE
46 .equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS
47 .equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE
48 .equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE
49 .equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE
50 .equ CPU_REG_DUMP_SIZE, CPU_WORD_SIZE
51
52#ifndef IMAGE_AT_EL3
53 .equ CPU_RESET_FUNC_SIZE, 0
Soby Mathewc704cbc2014-08-14 11:33:56 +010054#endif
Roberto Vargas67762d92018-05-01 09:54:54 +010055
56/* The power down core and cluster is needed only in BL31 */
57#ifndef IMAGE_BL31
58 .equ CPU_PWR_DWN_OPS_SIZE, 0
Soby Mathew8e2f2872014-08-14 12:49:05 +010059#endif
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000060
Roberto Vargas67762d92018-05-01 09:54:54 +010061/* Fields required to print errata status. */
62#if !REPORT_ERRATA
63 .equ CPU_ERRATA_FUNC_SIZE, 0
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000064#endif
Roberto Vargas67762d92018-05-01 09:54:54 +010065
66/* Only BL31 requieres mutual exclusion and printed flag. */
67#if !(REPORT_ERRATA && defined(IMAGE_BL31))
68 .equ CPU_ERRATA_LOCK_SIZE, 0
69 .equ CPU_ERRATA_PRINTED_SIZE, 0
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000070#endif
71
Roberto Vargas67762d92018-05-01 09:54:54 +010072#if !defined(IMAGE_BL31) || !CRASH_REPORTING
73 .equ CPU_REG_DUMP_SIZE, 0
Soby Mathew38b4bc92014-08-14 13:36:41 +010074#endif
Roberto Vargas67762d92018-05-01 09:54:54 +010075
76/*
77 * Define the offsets to the fields in cpu_ops structure.
78 * Every offset is defined based in the offset and size of the previous
79 * field.
80 */
81 .equ CPU_MIDR, 0
82 .equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE
83 .equ CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
84 .equ CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
85 .equ CPU_PWR_DWN_OPS, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
86 .equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
87 .equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
88 .equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
89 .equ CPU_REG_DUMP, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
90 .equ CPU_OPS_SIZE, CPU_REG_DUMP + CPU_REG_DUMP_SIZE
Achin Gupta4f6ad662013-10-25 09:08:21 +010091
Soby Mathewc704cbc2014-08-14 11:33:56 +010092 /*
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +000093 * Write given expressions as quad words
94 *
95 * _count:
96 * Write at least _count quad words. If the given number of
97 * expressions is less than _count, repeat the last expression to
98 * fill _count quad words in total
99 * _rest:
100 * Optional list of expressions. _this is for parameter extraction
101 * only, and has no significance to the caller
102 *
103 * Invoked as:
104 * fill_constants 2, foo, bar, blah, ...
Achin Gupta4f6ad662013-10-25 09:08:21 +0100105 */
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +0000106 .macro fill_constants _count:req, _this, _rest:vararg
107 .ifgt \_count
108 /* Write the current expression */
109 .ifb \_this
110 .error "Nothing to fill"
111 .endif
112 .quad \_this
113
114 /* Invoke recursively for remaining expressions */
115 .ifnb \_rest
116 fill_constants \_count-1, \_rest
117 .else
118 fill_constants \_count-1, \_this
119 .endif
120 .endif
121 .endm
122
123 /*
124 * Declare CPU operations
125 *
126 * _name:
127 * Name of the CPU for which operations are being specified
128 * _midr:
129 * Numeric value expected to read from CPU's MIDR
130 * _resetfunc:
131 * Reset function for the CPU. If there's no CPU reset function,
132 * specify CPU_NO_RESET_FUNC
Dimitris Papastamos914757c2018-03-12 14:47:09 +0000133 * _extra1:
134 * This is a placeholder for future per CPU operations. Currently,
135 * some CPUs use this entry to set a test function to determine if
136 * the workaround for CVE-2017-5715 needs to be applied or not.
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +0100137 * _extra2:
138 * This is a placeholder for future per CPU operations. Currently
139 * some CPUs use this entry to set a function to disable the
140 * workaround for CVE-2018-3639.
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +0000141 * _power_down_ops:
142 * Comma-separated list of functions to perform power-down
143 * operatios on the CPU. At least one, and up to
144 * CPU_MAX_PWR_DWN_OPS number of functions may be specified.
145 * Starting at power level 0, these functions shall handle power
146 * down at subsequent power levels. If there aren't exactly
147 * CPU_MAX_PWR_DWN_OPS functions, the last specified one will be
148 * used to handle power down at subsequent levels
149 */
Dimitris Papastamos914757c2018-03-12 14:47:09 +0000150 .macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +0100151 _extra1:req, _extra2:req, _power_down_ops:vararg
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +0000152 .section cpu_ops, "a"
153 .align 3
Soby Mathewc704cbc2014-08-14 11:33:56 +0100154 .type cpu_ops_\_name, %object
155 .quad \_midr
Roberto Vargase0e99462017-10-30 14:43:43 +0000156#if defined(IMAGE_AT_EL3)
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +0000157 .quad \_resetfunc
Soby Mathewc704cbc2014-08-14 11:33:56 +0100158#endif
Dimitris Papastamos914757c2018-03-12 14:47:09 +0000159 .quad \_extra1
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +0100160 .quad \_extra2
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900161#ifdef IMAGE_BL31
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +0000162 /* Insert list of functions */
163 fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
Soby Mathew8e2f2872014-08-14 12:49:05 +0100164#endif
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +0000165
166#if REPORT_ERRATA
167 .ifndef \_name\()_cpu_str
168 /*
169 * Place errata reported flag, and the spinlock to arbitrate access to
170 * it in the data section.
171 */
172 .pushsection .data
173 define_asm_spinlock \_name\()_errata_lock
174 \_name\()_errata_reported:
175 .word 0
176 .popsection
177
178 /* Place CPU string in rodata */
179 .pushsection .rodata
180 \_name\()_cpu_str:
181 .asciz "\_name"
182 .popsection
183 .endif
184
185 /*
186 * Weakly-bound, optional errata status printing function for CPUs of
187 * this class.
188 */
189 .weak \_name\()_errata_report
190 .quad \_name\()_errata_report
191
192#ifdef IMAGE_BL31
193 /* Pointers to errata lock and reported flag */
194 .quad \_name\()_errata_lock
195 .quad \_name\()_errata_reported
196#endif
197#endif
198
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900199#if defined(IMAGE_BL31) && CRASH_REPORTING
Soby Mathew38b4bc92014-08-14 13:36:41 +0100200 .quad \_name\()_cpu_reg_dump
201#endif
Soby Mathewc704cbc2014-08-14 11:33:56 +0100202 .endm
Dan Handleyea596682015-04-01 17:34:24 +0100203
Dimitris Papastamos914757c2018-03-12 14:47:09 +0000204 .macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
205 _power_down_ops:vararg
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +0100206 declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, \
Dimitris Papastamos914757c2018-03-12 14:47:09 +0000207 \_power_down_ops
208 .endm
209
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +0100210 .macro declare_cpu_ops_wa _name:req, _midr:req, \
211 _resetfunc:req, _extra1:req, _extra2:req, \
212 _power_down_ops:vararg
Dimitris Papastamos914757c2018-03-12 14:47:09 +0000213 declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +0100214 \_extra1, \_extra2, \_power_down_ops
Dimitris Papastamos914757c2018-03-12 14:47:09 +0000215 .endm
216
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +0000217#if REPORT_ERRATA
218 /*
219 * Print status of a CPU errata
220 *
221 * _chosen:
222 * Identifier indicating whether or not a CPU errata has been
223 * compiled in.
224 * _cpu:
225 * Name of the CPU
226 * _id:
227 * Errata identifier
228 * _rev_var:
229 * Register containing the combined value CPU revision and variant
230 * - typically the return value of cpu_get_rev_var
231 */
232 .macro report_errata _chosen, _cpu, _id, _rev_var=x8
233 /* Stash a string with errata ID */
234 .pushsection .rodata
235 \_cpu\()_errata_\_id\()_str:
236 .asciz "\_id"
237 .popsection
238
239 /* Check whether errata applies */
240 mov x0, \_rev_var
Jonathan Wrightefb1f332018-03-28 15:52:03 +0100241 /* Shall clobber: x0-x7 */
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +0000242 bl check_errata_\_id
243
244 .ifeq \_chosen
245 /*
246 * Errata workaround has not been compiled in. If the errata would have
247 * applied had it been compiled in, print its status as missing.
248 */
249 cbz x0, 900f
250 mov x0, #ERRATA_MISSING
251 .endif
252900:
253 adr x1, \_cpu\()_cpu_str
254 adr x2, \_cpu\()_errata_\_id\()_str
255 bl errata_print_msg
256 .endm
257#endif
258
Dan Handleyea596682015-04-01 17:34:24 +0100259#endif /* __CPU_MACROS_S__ */
Dimitris Papastamos780cc952018-03-12 13:27:02 +0000260
261 /*
262 * This macro is used on some CPUs to detect if they are vulnerable
263 * to CVE-2017-5715.
264 */
265 .macro cpu_check_csv2 _reg _label
266 mrs \_reg, id_aa64pfr0_el1
267 ubfx \_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH
268 /*
269 * If the field equals to 1 then branch targets trained in one
270 * context cannot affect speculative execution in a different context.
271 */
272 cmp \_reg, #1
273 beq \_label
274 .endm
Deepak Pandeyb5615362018-10-11 13:44:43 +0530275
276 /*
277 * Helper macro that reads the part number of the current
278 * CPU and jumps to the given label if it matches the CPU
279 * MIDR provided.
280 *
281 * Clobbers x0.
282 */
283 .macro jump_if_cpu_midr _cpu_midr, _label
284 mrs x0, midr_el1
285 ubfx x0, x0, MIDR_PN_SHIFT, #12
286 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
287 b.eq \_label
288 .endm