blob: 353faf8a2dce56a27700831aa75054e4a7eb458e [file] [log] [blame]
developera84a44a2020-08-19 17:20:15 +08001/*
2 * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/debug.h>
8#include <common/runtime_svc.h>
developerceb197f2021-04-20 12:53:15 +08009#include <mtk_apusys.h>
developerafa342e2020-12-14 17:41:08 +080010#include <mtk_sip_svc.h>
11#include <mt_spm_vcorefs.h>
developer4d819312021-07-05 20:42:09 +080012#include <plat_dfd.h>
developerafa342e2020-12-14 17:41:08 +080013#include "plat_sip_calls.h"
developera84a44a2020-08-19 17:20:15 +080014
15uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
16 u_register_t x1,
17 u_register_t x2,
18 u_register_t x3,
19 u_register_t x4,
20 void *cookie,
21 void *handle,
22 u_register_t flags)
23{
developerafa342e2020-12-14 17:41:08 +080024 uint64_t ret;
developerceb197f2021-04-20 12:53:15 +080025 uint32_t rnd_val0 = 0U;
developera84a44a2020-08-19 17:20:15 +080026
27 switch (smc_fid) {
developerafa342e2020-12-14 17:41:08 +080028 case MTK_SIP_VCORE_CONTROL_ARCH32:
29 case MTK_SIP_VCORE_CONTROL_ARCH64:
30 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4);
31 SMC_RET2(handle, ret, x4);
32 break;
developerceb197f2021-04-20 12:53:15 +080033 case MTK_SIP_APUSYS_CONTROL_AARCH32:
34 case MTK_SIP_APUSYS_CONTROL_AARCH64:
35 ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0);
36 SMC_RET2(handle, ret, rnd_val0);
37 break;
developer4d819312021-07-05 20:42:09 +080038 case MTK_SIP_KERNEL_DFD_AARCH32:
39 case MTK_SIP_KERNEL_DFD_AARCH64:
40 ret = dfd_smc_dispatcher(x1, x2, x3, x4);
41 SMC_RET1(handle, ret);
42 break;
developera84a44a2020-08-19 17:20:15 +080043 default:
44 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
45 break;
46 }
47
48 SMC_RET1(handle, SMC_UNK);
49}