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Etienne Carriere010dd1f2017-11-05 22:56:41 +01001/*
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +00002 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
Etienne Carriere010dd1f2017-11-05 22:56:41 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef CORTEX_A17_H
8#define CORTEX_A17_H
Etienne Carriere010dd1f2017-11-05 22:56:41 +01009
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000010#include <lib/utils_def.h>
11
Etienne Carriere010dd1f2017-11-05 22:56:41 +010012/*******************************************************************************
13 * Cortex-A17 midr with version/revision set to 0
14 ******************************************************************************/
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000015#define CORTEX_A17_MIDR U(0x410FC0E0)
Etienne Carriere010dd1f2017-11-05 22:56:41 +010016
17/*******************************************************************************
18 * CPU Auxiliary Control register specific definitions.
19 ******************************************************************************/
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000020#define CORTEX_A17_ACTLR_SMP_BIT (U(1) << 6)
Etienne Carriere010dd1f2017-11-05 22:56:41 +010021
Ambroise Vincent8cf9eef2019-02-28 16:23:53 +000022/*******************************************************************************
23 * Implementation defined register specific definitions.
24 ******************************************************************************/
25#define CORTEX_A17_IMP_DEF_REG1 p15, 0, c15, c0, 1
26
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000027#endif /* CORTEX_A17_H */