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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Roberto Vargas1a6eed32018-02-12 12:36:17 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Sathees Balya50905c72018-10-05 13:30:59 +01007#ifndef FVP_PWRC_H
8#define FVP_PWRC_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
10/* FVP Power controller register offset etc */
Sathees Balya50905c72018-10-05 13:30:59 +010011#define PPOFFR_OFF U(0x0)
12#define PPONR_OFF U(0x4)
13#define PCOFFR_OFF U(0x8)
14#define PWKUPR_OFF U(0xc)
15#define PSYSR_OFF U(0x10)
Achin Gupta4f6ad662013-10-25 09:08:21 +010016
Sathees Balya50905c72018-10-05 13:30:59 +010017#define PWKUPR_WEN BIT_32(31)
Achin Gupta4f6ad662013-10-25 09:08:21 +010018
Sathees Balya50905c72018-10-05 13:30:59 +010019#define PSYSR_AFF_L2 BIT_32(31)
20#define PSYSR_AFF_L1 BIT_32(30)
21#define PSYSR_AFF_L0 BIT_32(29)
22#define PSYSR_WEN BIT_32(28)
23#define PSYSR_PC BIT_32(27)
24#define PSYSR_PP BIT_32(26)
Achin Gupta4f6ad662013-10-25 09:08:21 +010025
26#define PSYSR_WK_SHIFT 24
Soby Mathew2ae23192015-04-30 12:27:41 +010027#define PSYSR_WK_WIDTH 0x2
Sathees Balya50905c72018-10-05 13:30:59 +010028#define PSYSR_WK_MASK ((1U << PSYSR_WK_WIDTH) - 1U)
29#define PSYSR_WK(x) ((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK
Achin Gupta4f6ad662013-10-25 09:08:21 +010030
Sathees Balya50905c72018-10-05 13:30:59 +010031#define WKUP_COLD U(0x0)
32#define WKUP_RESET U(0x1)
33#define WKUP_PPONR U(0x2)
34#define WKUP_GICREQ U(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +010035
Sathees Balya50905c72018-10-05 13:30:59 +010036#define PSYSR_INVALID U(0xffffffff)
Achin Gupta4f6ad662013-10-25 09:08:21 +010037
Julius Werner53456fc2019-07-09 13:49:11 -070038#ifndef __ASSEMBLER__
Achin Gupta4f6ad662013-10-25 09:08:21 +010039
Antonio Nino Diazf13d09a2019-01-23 21:50:09 +000040#include <stdint.h>
41
Achin Gupta4f6ad662013-10-25 09:08:21 +010042/*******************************************************************************
43 * Function & variable prototypes
44 ******************************************************************************/
Roberto Vargas1a6eed32018-02-12 12:36:17 +000045void fvp_pwrc_write_pcoffr(u_register_t mpidr);
46void fvp_pwrc_write_ppoffr(u_register_t mpidr);
47void fvp_pwrc_write_pponr(u_register_t mpidr);
48void fvp_pwrc_set_wen(u_register_t mpidr);
49void fvp_pwrc_clr_wen(u_register_t mpidr);
50unsigned int fvp_pwrc_read_psysr(u_register_t mpidr);
51unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +010052
Julius Werner53456fc2019-07-09 13:49:11 -070053#endif /*__ASSEMBLER__*/
Achin Gupta4f6ad662013-10-25 09:08:21 +010054
Sathees Balya50905c72018-10-05 13:30:59 +010055#endif /* FVP_PWRC_H */