| Bharat Gooty | 29e3eb9 | 2020-09-24 15:29:28 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019 - 2021, Broadcom |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SR_USB_H |
| 8 | #define SR_USB_H |
| 9 | |
| 10 | #define CDRU_PM_RESET_N_R BIT(CDRU_MISC_RESET_CONTROL__CDRU_PM_RESET_N_R) |
| 11 | #define CDRU_USBSS_RESET_N BIT(CDRU_MISC_RESET_CONTROL__CDRU_USBSS_RESET_N) |
| 12 | #define CDRU_MISC_CLK_USBSS \ |
| 13 | BIT(CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_USBSS_CLK_EN_R) |
| 14 | |
| 15 | #define RESCAL_I_RSTB BIT(26) |
| 16 | #define RESCAL_I_PWRDNB BIT(27) |
| 17 | |
| 18 | #define DRDU3_U3PHY_CTRL 0x68500014 |
| 19 | #define PHY_RESET BIT(1) |
| 20 | #define POR_RESET BIT(28) |
| 21 | #define MDIO_RESET BIT(29) |
| 22 | |
| 23 | #define DRDU3_PWR_CTRL 0x6850002c |
| 24 | #define POWER_CTRL_OVRD BIT(2) |
| 25 | |
| 26 | #define USB3H_U3PHY_CTRL 0x68510014 |
| 27 | #define USB3H_U3SOFT_RST_N BIT(30) |
| 28 | |
| 29 | #define USB3H_PWR_CTRL 0x68510028 |
| 30 | |
| 31 | #define USB3_PHY_MDIO_BLOCK_BASE_REG 0x1f |
| 32 | #define BDC_AXI_SOFT_RST_N_OFFSET 0 |
| 33 | #define XHC_AXI_SOFT_RST_N_OFFSET 1 |
| 34 | #define MDIO_BUS_ID 3 |
| 35 | #define USB3H_PHY_ID 5 |
| 36 | #define USB3DRD_PHY_ID 2 |
| 37 | |
| 38 | #define USB3_PHY_RXPMD_BLOCK_BASE 0x8020 |
| 39 | #define USB3_PHY_RXPMD_REG1 0x1 |
| 40 | #define USB3_PHY_RXPMD_REG2 0x2 |
| 41 | #define USB3_PHY_RXPMD_REG5 0x5 |
| 42 | #define USB3_PHY_RXPMD_REG7 0x7 |
| 43 | |
| 44 | #define USB3_PHY_TXPMD_BLOCK_BASE 0x8040 |
| 45 | #define USB3_PHY_TXPMD_REG1 0x1 |
| 46 | #define USB3_PHY_TXPMD_REG2 0x2 |
| 47 | |
| 48 | #define USB3_PHY_ANA_BLOCK_BASE 0x8090 |
| 49 | #define USB3_PHY_ANA_REG0 0x0 |
| 50 | #define USB3_PHY_ANA_REG1 0x1 |
| 51 | #define USB3_PHY_ANA_REG2 0x2 |
| 52 | #define USB3_PHY_ANA_REG5 0x5 |
| 53 | #define USB3_PHY_ANA_REG8 0x8 |
| 54 | #define USB3_PHY_ANA_REG11 0xb |
| 55 | |
| 56 | #define USB3_PHY_AEQ_BLOCK_BASE 0x80e0 |
| 57 | #define USB3_PHY_AEQ_REG1 0x1 |
| 58 | #define USB3_PHY_AEQ_REG3 0x3 |
| 59 | |
| 60 | #ifdef USB_DMA_COHERENT |
| 61 | #define DRDU3_U3XHC_SOFT_RST_N BIT(31) |
| 62 | #define DRDU3_U3BDC_SOFT_RST_N BIT(30) |
| 63 | |
| 64 | #define DRDU3_SOFT_RESET_CTRL 0x68500030 |
| 65 | #define DRDU3_XHC_AXI_SOFT_RST_N BIT(1) |
| 66 | #define DRDU3_BDC_AXI_SOFT_RST_N BIT(0) |
| 67 | |
| 68 | #define DRDU2_PHY_CTRL 0x6852000c |
| 69 | #define DRDU2_U2SOFT_RST_N BIT(29) |
| 70 | |
| 71 | #define USB3H_SOFT_RESET_CTRL 0x6851002c |
| 72 | #define USB3H_XHC_AXI_SOFT_RST_N BIT(1) |
| 73 | |
| 74 | #define DRDU2_SOFT_RESET_CTRL 0x68520020 |
| 75 | #define DRDU2_BDC_AXI_SOFT_RST_N BIT(0) |
| 76 | |
| 77 | #define DRD2U3H_XHC_REGS_AXIWRA 0x68511c08 |
| 78 | #define DRD2U3H_XHC_REGS_AXIRDA 0x68511c0c |
| 79 | #define DRDU2D_BDC_REGS_AXIWRA 0x68521c08 |
| 80 | #define DRDU2D_BDC_REGS_AXIRDA 0x68521c0c |
| 81 | #define DRDU3H_XHC_REGS_AXIWRA 0x68501c08 |
| 82 | #define DRDU3H_XHC_REGS_AXIRDA 0x68501c0c |
| 83 | #define DRDU3D_BDC_REGS_AXIWRA 0x68502c08 |
| 84 | #define DRDU3D_BDC_REGS_AXIRDA 0x68502c0c |
| 85 | /* cacheable write-back, allocate on both reads and writes */ |
| 86 | #define USBAXI_AWCACHE 0xf |
| 87 | #define USBAXI_ARCACHE 0xf |
| 88 | /* non-secure */ |
| 89 | #define USBAXI_AWPROT 0x8 |
| 90 | #define USBAXI_ARPROT 0x8 |
| 91 | #define USBAXIWR_SA_VAL ((USBAXI_AWCACHE << 4 | USBAXI_AWPROT) << 0) |
| 92 | #define USBAXIWR_SA_MASK ((0xf << 4 | 0xf) << 0) |
| 93 | #define USBAXIWR_UA_VAL ((USBAXI_AWCACHE << 4 | USBAXI_AWPROT) << 16) |
| 94 | #define USBAXIWR_UA_MASK ((0xf << 4 | 0xf) << 0) |
| 95 | #define USBAXIRD_SA_VAL ((USBAXI_ARCACHE << 4 | USBAXI_ARPROT) << 0) |
| 96 | #define USBAXIRD_SA_MASK ((0xf << 4 | 0xf) << 0) |
| 97 | #define USBAXIRD_UA_VAL ((USBAXI_ARCACHE << 4 | USBAXI_ARPROT) << 16) |
| 98 | #define USBAXIRD_UA_MASK ((0xf << 4 | 0xf) << 0) |
| 99 | #endif /* USB_DMA_COHERENT */ |
| 100 | |
| 101 | #define ICFG_DRDU3_SID_CTRL 0x6850001c |
| 102 | #define ICFG_USB3H_SID_CTRL 0x6851001c |
| 103 | #define ICFG_DRDU2_SID_CTRL 0x68520010 |
| 104 | #define ICFG_USB_SID_SHIFT 5 |
| 105 | #define ICFG_USB_SID_AWADDR_OFFSET 0x0 |
| 106 | #define ICFG_USB_SID_ARADDR_OFFSET 0x4 |
| 107 | |
| 108 | #define USBIC_GPV_BASE 0x68600000 |
| 109 | #define USBIC_GPV_SECURITY0 (USBIC_GPV_BASE + 0x8) |
| 110 | #define USBIC_GPV_SECURITY0_FIELD BIT(0) |
| 111 | #define USBIC_GPV_SECURITY1 (USBIC_GPV_BASE + 0xc) |
| 112 | #define USBIC_GPV_SECURITY1_FIELD (BIT(0) | BIT(1)) |
| 113 | #define USBIC_GPV_SECURITY2 (USBIC_GPV_BASE + 0x10) |
| 114 | #define USBIC_GPV_SECURITY2_FIELD (BIT(0) | BIT(1)) |
| 115 | #define USBIC_GPV_SECURITY4 (USBIC_GPV_BASE + 0x18) |
| 116 | #define USBIC_GPV_SECURITY4_FIELD BIT(0) |
| 117 | #define USBIC_GPV_SECURITY10 (USBIC_GPV_BASE + 0x30) |
| 118 | #define USBIC_GPV_SECURITY10_FIELD (0x7 << 0) |
| 119 | |
| 120 | #define USBSS_TZPCDECPROT_BASE 0x68540800 |
| 121 | #define USBSS_TZPCDECPROT0set (USBSS_TZPCDECPROT_BASE + 0x4) |
| 122 | #define USBSS_TZPCDECPROT0clr (USBSS_TZPCDECPROT_BASE + 0x8) |
| 123 | #define DECPROT0_USBSS_DRD2U3H BIT(3) |
| 124 | #define DECPROT0_USBSS_DRDU2H BIT(2) |
| 125 | #define DECPROT0_USBSS_DRDU3D BIT(1) |
| 126 | #define DECPROT0_USBSS_DRDU2D BIT(0) |
| 127 | #define USBSS_TZPCDECPROT0 \ |
| 128 | (DECPROT0_USBSS_DRD2U3H | \ |
| 129 | DECPROT0_USBSS_DRDU2H | \ |
| 130 | DECPROT0_USBSS_DRDU3D | \ |
| 131 | DECPROT0_USBSS_DRDU2D) |
| 132 | |
| 133 | int32_t usb_device_init(unsigned int); |
| 134 | |
| 135 | #endif /* SR_USB_H */ |